Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
PCU – iLB – 8259 Programmable Interrupt Controllers (PIC)
1278
Datasheet
32.1.2.4
ICW4
The final write in the sequence (ICW4) must be programmed for both controllers. At
the very least, ICW4.MM must be set to a 1 to indicate that the controllers are
operating in an Intel Architecture-based system.
the very least, ICW4.MM must be set to a 1 to indicate that the controllers are
operating in an Intel Architecture-based system.
32.1.3
Operation Command Words (OCW)
These command words reprogram the Interrupt controller to operate in various
interrupt modes.
interrupt modes.
•
OCW1 masks and unmasks interrupt lines.
•
OCW2 controls the rotation of interrupt priorities when in rotating priority mode,
and controls the EOI function.
and controls the EOI function.
•
OCW3 sets up ISR/IRR reads, enables/disables the special mask mode (SMM), and
enables/disables polled interrupt mode.
enables/disables polled interrupt mode.
32.1.4
Modes of Operation
32.1.4.1
Fully Nested Mode
In this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being
the highest. When an interrupt is acknowledged, the highest priority request is
determined and its vector placed on the bus. Additionally, the ISR for the interrupt is
set. This ISR bit remains set until: the processor issues an EOI command immediately
before returning from the service routine; or if in AEOI mode, on the trailing edge of
the second INTA#. While the ISR bit is set, all further interrupts of the same or lower
priority are inhibited, while higher levels generate another interrupt.
the highest. When an interrupt is acknowledged, the highest priority request is
determined and its vector placed on the bus. Additionally, the ISR for the interrupt is
set. This ISR bit remains set until: the processor issues an EOI command immediately
before returning from the service routine; or if in AEOI mode, on the trailing edge of
the second INTA#. While the ISR bit is set, all further interrupts of the same or lower
priority are inhibited, while higher levels generate another interrupt.
Interrupt priorities can be changed in the rotating priority mode.
32.1.4.2
Special Fully-Nested Mode
This mode is used in the case of a system where cascading is used, and the priority has
to be conserved within each slave. In this case, the special fully-nested mode is
programmed to the master controller. This mode is similar to the fully-nested mode
with the following exceptions:
to be conserved within each slave. In this case, the special fully-nested mode is
programmed to the master controller. This mode is similar to the fully-nested mode
with the following exceptions:
•
When an interrupt request from a certain slave is in service, this slave is not locked
out from the master's priority logic and further interrupt requests from higher
priority interrupts within the slave are recognized by the master and initiate
interrupts to the processor. In the normal-nested mode, a slave is masked out
when its request is in service.
out from the master's priority logic and further interrupt requests from higher
priority interrupts within the slave are recognized by the master and initiate
interrupts to the processor. In the normal-nested mode, a slave is masked out
when its request is in service.
•
When exiting the Interrupt Service routine, software has to check whether the
interrupt serviced was the only one from that slave. This is done by sending a Non-
Specific EOI command to the slave and then reading its ISR. If it is 0, a non-
specific EOI can also be sent to the master.
interrupt serviced was the only one from that slave. This is done by sending a Non-
Specific EOI command to the slave and then reading its ISR. If it is 0, a non-
specific EOI can also be sent to the master.