Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
PCU – iLB – 8259 Programmable Interrupt Controllers (PIC)
1280
Datasheet
If an ELCR bit is 0, an interrupt request will be recognized by a low-to-high transition
on the corresponding IRQ input. The IRQ input can remain high without generating
another interrupt. If an ELCR bit is 1, an interrupt request will be recognized by a high
level on the corresponding IRQ input and there is no need for an edge detection. The
interrupt request must be removed before the EOI command is issued to prevent a
second interrupt from occurring.
on the corresponding IRQ input. The IRQ input can remain high without generating
another interrupt. If an ELCR bit is 1, an interrupt request will be recognized by a high
level on the corresponding IRQ input and there is no need for an edge detection. The
interrupt request must be removed before the EOI command is issued to prevent a
second interrupt from occurring.
In both the edge and level triggered modes, the IRQ inputs must remain active until
after the falling edge of the first internal INTA#. If the IRQ input goes inactive before
this time, a default IRQ7 vector is returned.
after the falling edge of the first internal INTA#. If the IRQ input goes inactive before
this time, a default IRQ7 vector is returned.
32.1.5
End of Interrupt (EOI) Operations
An EOI can occur in one of two fashions: by a command word write issued to the PIC
before returning from a service routine, the EOI command; or automatically when the
ICW4.AEOI bit is set to 1.
before returning from a service routine, the EOI command; or automatically when the
ICW4.AEOI bit is set to 1.
32.1.5.1
Normal End of Interrupt
In normal EOI, software writes an EOI command before leaving the interrupt service
routine to mark the interrupt as completed. There are two forms of EOI commands:
Specific and Non-Specific. When a Non-Specific EOI command is issued, the PIC clears
the highest ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of
operation of the PIC within the processor, as the interrupt being serviced currently is
the interrupt entered with the interrupt acknowledge. When the PIC is operated in
modes that preserve the fully nested structure, software can determine which ISR bit
to clear by issuing a Specific EOI.
routine to mark the interrupt as completed. There are two forms of EOI commands:
Specific and Non-Specific. When a Non-Specific EOI command is issued, the PIC clears
the highest ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of
operation of the PIC within the processor, as the interrupt being serviced currently is
the interrupt entered with the interrupt acknowledge. When the PIC is operated in
modes that preserve the fully nested structure, software can determine which ISR bit
to clear by issuing a Specific EOI.
An ISR bit that is masked is not cleared by a Non-Specific EOI if the PIC is in the special
mask mode. An EOI command must be issued for both the master and slave controller.
mask mode. An EOI command must be issued for both the master and slave controller.
32.1.5.2
Automatic End of Interrupt Mode
In this mode, the PIC automatically performs a Non-Specific EOI operation at the
trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this
mode should be used only when a nested multi-level interrupt structure is not required
within a single PIC. The AEOI mode can only be used in the master controller and not
the slave controller.
trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this
mode should be used only when a nested multi-level interrupt structure is not required
within a single PIC. The AEOI mode can only be used in the master controller and not
the slave controller.
Note:
Both the master and slave PICs have an AEOI bit: MICW4.AEOI and SICW4.AEOI
respectively. Only the MICW4.AEOI bit should be set by software. The SICW4.AEOI bit
should not be set by software.
respectively. Only the MICW4.AEOI bit should be set by software. The SICW4.AEOI bit
should not be set by software.