Intel N2820 FH8065301616603 Data Sheet

Intel

Product codes

FH8065301616603

Datasheet

381

USB Host Controller Interfaces (xHCI, EHCI)

4D0h

4D3h

“Port 6 Status and Control USB2 (PORTSC6USB2)—Offset 4D0h” on page 412

000002A0h

4D4h

4D7h

“Port 6 Power Management Status and Control USB2 (PORTPMSC6USB2)—Offset

4D4h” on page 414

00000000h

4DCh

4DFh

“Port X Hardware LPM Control Register (PORTHLPM6)—Offset 4DCh” on page 414

00000000h

4E0h

4E3h

“Port 1 Status and Control USB3 (PORTSC1USB3)—Offset 4E0h” on page 415

000002A0h

4E4h

4E7h

“Port 1 Power Management Status and Control USB3 (PORTPMSC1USB3)—Offset

4E4h” on page 417

00000000h

4E8h

4EBh

“Port 1 Link Info (PORTLI1)—Offset 4E8h” on page 418

00000000h

2000h

2003h

“Microframe Index (MFINDEX)—Offset 2000h” on page 418

00000000h

2020h

2023h

“Interrupter 1 Management (IMAN1)—Offset 2020h” on page 419

00000000h

2024h

2027h

“Interrupter 1 Moderation (IMOD1)—Offset 2024h” on page 419

00000FA0h

2028h

202Bh

“Event Ring Segment Table Size 1 (ERSTSZ1)—Offset 2028h” on page 420

00000000h

2030h

2033h

“Event Ring Segment Table Base Address Low 1 (ERSTBA_LO1)—Offset 2030h” on

00000000h

2034h

2037h

“Event Ring Segment Table Base Address High 1 (ERSTBA_HI1)—Offset 2034h” on

00000000h

2038h

203Bh

“Event Ring Dequeue Pointer Low 1 (ERDP_LO1)—Offset 2038h” on page 421

00000000h

203Ch

203Fh

“Event Ring Dequeue Pointer High 1 (ERDP_HI1)—Offset 203Ch” on page 422

00000000h

2040h

2043h

“Interrupter 2 Management (IMAN2)—Offset 2040h” on page 422

00000000h

2044h

2047h

“Interrupter 2 Moderation (IMOD2)—Offset 2044h” on page 423

00000FA0h

2048h

204Bh

“Event Ring Segment Table Size 2 (ERSTSZ2)—Offset 2048h” on page 423

00000000h

2050h

2053h

“Event Ring Segment Table Base Address Low 2 (ERSTBA_LO2)—Offset 2050h” on

00000000h

2054h

2057h

“Event Ring Segment Table Base Address High 2 (ERSTBA_HI2)—Offset 2054h” on

00000000h

2058h

205Bh

“Event Ring Dequeue Pointer Low 2 (ERDP_LO2)—Offset 2058h” on page 425

00000000h

205Ch

205Fh

“Event Ring Dequeue Pointer High 2 (ERDP_HI2)—Offset 205Ch” on page 425

00000000h

2060h

2063h

“Interrupter 3 Management (IMAN3)—Offset 2060h” on page 426

00000000h

2064h

2067h

“Interrupter 3 Moderation (IMOD3)—Offset 2064h” on page 426

00000FA0h

2068h

206Bh

“Event Ring Segment Table Size 3 (ERSTSZ3)—Offset 2068h” on page 427

00000000h

2070h

2073h

“Event Ring Segment Table Base Address Low 3 (ERSTBA_LO3)—Offset 2070h” on

00000000h

2074h

2077h

“Event Ring Segment Table Base Address High 3 (ERSTBA_HI3)—Offset 2074h” on

00000000h

2078h

207Bh

“Event Ring Dequeue Pointer Low 3 (ERDP_LO3)—Offset 2078h” on page 428

00000000h

207Ch

207Fh

“Event Ring Dequeue Pointer High 3 (ERDP_HI3)—Offset 207Ch” on page 429

00000000h

2080h

2083h

“Interrupter 4 Management (IMAN4)—Offset 2080h” on page 429

00000000h

2084h

2087h

“Interrupter 4 Moderation (IMOD4)—Offset 2084h” on page 430

00000FA0h

2088h

208Bh

“Event Ring Segment Table Size 4 (ERSTSZ4)—Offset 2088h” on page 430

00000000h

2090h

2093h

“Event Ring Segment Table Base Address Low 4 (ERSTBA_LO4)—Offset 2090h” on

00000000h

2094h

2097h

“Event Ring Segment Table Base Address High 4 (ERSTBA_HI4)—Offset 2094h” on

00000000h

Table 120.

Summary of USB xHCI Memory Mapped I/O Registers—MBAR (Continued)

Offset Start

Offset End

Register ID—Description

Default

Value