Intel N2820 FH8065301616603 Data Sheet

Product codes
FH8065301616603
Page of 1294
Datasheet
53
Mapping Address Spaces
Processor writes to the 64 KB (each) PROM ‘E’ and ‘F’ segments (E0000h–EFFFFh and 
F0000h–FFFFFh) always target DRAM. The BMISC register is used to direct CPU core 
reads in these two segments to DRAM or the IO fabric (MMIO).
CPU core accesses to the 128 KB VGA/CSEG range (A0000h–BFFFFh) can target DRAM 
or the IO fabric (MMIO). The target is selected with the BMISC.ABSEGINDRAM register.
4.1.1.3
Additional Mappings
There are two additional mappings available in the Processor Transaction Router:
SMM range
Non-snoop range
SMI handlers running on a CPU core execute out of SMM memory. To protect this 
memory from non-CPU core access, the SMM Range (BSMMRRL-BSMMRRH) may be 
programmed anywhere in low or high DRAM space (1 MB aligned). This range will only 
allow accesses from the CPU cores.
To prevent snoops of the CPU cores when DMA devices access a specific memory 
region, the Non-Snoopable Memory range (BNOCACHE.Lower-BNOCACHE.Upper) 
can be programmed anywhere in physical address space. This range is enabled via the 
BNOCACHECTL register’s enable bit (BNOCACHECTL.Enable).
Figure 5.
Physical Address Space – SMM and Non-Snoop Mappings
64 GB
Physical Address 
Space
BNOCACHE.Upper...
BNOCACHE.Lower...
0
Non-Snoopable 
Memory
Low or High DRAM in 
Physical Space
BSMMRRH (SMM Range Hi)
BSMMRRL (SMM Range Lo)
SMM Range