Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
Datasheet
55
Mapping Address Spaces
4.2.1
Processor Transaction Router IO Map
The processor claims IO transactions for VGA/Extended VGA found in the display/
graphics interface. It also claims the two 32-bit registers at port CF8h and CFCh used
to access PCI configuration space.
graphics interface. It also claims the two 32-bit registers at port CF8h and CFCh used
to access PCI configuration space.
4.2.2
IO Fabric IO Map
4.2.2.1
PCU Fixed IO Address Ranges
The following table shows the fixed IO space ranges seen by a processor.
4.2.2.2
Variable IO Address Ranges
shows the variable IO decode ranges. They are set using base address
registers (BARs) or other similar means. Plug-and-play (PnP) software (PCI/ACPI) can
use their configuration mechanisms to set and adjust these values.
use their configuration mechanisms to set and adjust these values.
Warning: The variable IO ranges should not be set to conflict with other IO ranges. There will be
unpredictable results if the configuration software allows conflicts to occur. Hardware
does not check for conflicts.
does not check for conflicts.
Table 35. Fixed IO Ranges in the Platform Controller Unit (PCU)
Device
IO Address
Comments
8259 Master
20h–21h, 24h–25h, 28h–29h,
2Ch–2Dh, 30h–31h, 34h–35h,
38h–39-, 3Ch–3Dh
8254s
40h–43h, 50h–53h
PS2 Control
60h, 64h
NMI Controller
61h, 63h, 65h, 67h
RTC
70h–77h
Port 80h
80h–83h
Init Register
92h
8259 Slave
A0h–A1h, A4h–A5h, A8h–A9h,
ACh–ADh, B0h–B1h, B4h–B5h,
B8h–B9h, BCh–BDh, 4D0h–
4D1h
PCU UART
3F8h–3FFh
Reset Control
CF9h
Overlaps PCI IO registers
Active Power Management
B2h–B3h
Table 36. Movable IO Ranges Decoded by PCI Devices on the IO Fabric (Sheet 1 of 2)
Device
Size
(bytes)
Target
SATA
See SATA register map for details.
ACPI Power Management (PCU)
128
ACPI_BASE_ADDR (PM1BLK): PCI[B:0,D:31,F:0] + 40h