Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
Datasheet
701
Low Power Engine (LPE) for Audio (I
2
S)
accumulate unit also supports multiplication of 32-bit values from LPE_OR registers by
16-bit values from LPE_PR registers, with the 48-bit result written or accumulated in
the LPE_OR register. The instructions for the DSP subsystems are built from operations
that are divided into two sets: the slot 0 set and the slot 1 set. In each execution cycle,
zero or one operations from each set can be executed independently according to the
static bundling expressed in the machine code.
16-bit values from LPE_PR registers, with the 48-bit result written or accumulated in
the LPE_OR register. The instructions for the DSP subsystems are built from operations
that are divided into two sets: the slot 0 set and the slot 1 set. In each execution cycle,
zero or one operations from each set can be executed independently according to the
static bundling expressed in the machine code.
16.3.2
Memory Architecture
The LPE core is configured to use local memory and local caches. It has 80KB of
Instruction Closely Coupled Memory (CCM), 160KB of Data CCM, 48KB of Instruction
Cache and 96KB of Data Cache. The LPE core also has access to 4KB of mailbox
memory and external DRAM.
Instruction Closely Coupled Memory (CCM), 160KB of Data CCM, 48KB of Instruction
Cache and 96KB of Data Cache. The LPE core also has access to 4KB of mailbox
memory and external DRAM.
Figure 22. Memory Connections for LPE
Prefetch buffer
(8x128B)
LPE Core
Instruction
CCM (80KB)
I-Cache
Data Array
(48KB)
Data
CCM (160KB)
D-Cache
Data array
(96KB)
Bridge
LPE shim
registers
Mailbox
memory
(4KB)
Audio
Fabric