Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
Low Power Engine (LPE) for Audio (I
2
S)
704
Datasheet
16.4.3.1
Audio S0ix Low Power Mode Entry
•
S0i1 and S0i2 entry are identical from the audio subsystem perspective. The choice
between S0i1 and S0i2 is decided by the latency that can be tolerated. For MP3
codec playback the system uses S0i2.
between S0i1 and S0i2 is decided by the latency that can be tolerated. For MP3
codec playback the system uses S0i2.
•
As part of S0ix entry decision making, SCU firmware needs to comprehend the
frequency requirements of the audio core and the latency tolerance (LTR) as
reported by audio firmware to SCU firmware (by means of the IPC). The audio core
frequency requirement has to be either 19.2 or 38.4 MHz for the system to enter
into S0ix with audio ON. Similarly the LTR reported earlier by audio firmware has to
allow S0ix entry.
frequency requirements of the audio core and the latency tolerance (LTR) as
reported by audio firmware to SCU firmware (by means of the IPC). The audio core
frequency requirement has to be either 19.2 or 38.4 MHz for the system to enter
into S0ix with audio ON. Similarly the LTR reported earlier by audio firmware has to
allow S0ix entry.
16.4.4
External Timer
This timer always runs from SSP clock (before M/N divider) at 19.2/25MHz. The timer
starts running once the run bit (refer to the External timer register definition for
details) is set and the clear bit is cleared.
starts running once the run bit (refer to the External timer register definition for
details) is set and the clear bit is cleared.
The timer generates an Interrupt pulse when the counter value matches the “match”
value. The interrupt does not get generated if the match value is set to “0”. The timer
runs in free running mode and rolls over after all 32 bits have become all 1’s.
value. The interrupt does not get generated if the match value is set to “0”. The timer
runs in free running mode and rolls over after all 32 bits have become all 1’s.
The timer continues to run as long as the run bit is set. Once the run bit is cleared the
timer holds the current value. The clear bit needs to be set to restart the timer from
“0”.
timer holds the current value. The clear bit needs to be set to restart the timer from
“0”.
16.5
Clocks
16.5.1
Clock Frequencies
shows the clock frequency options for the Audio functional blocks.
Table 126. Clock Frequencies
Clock
Frequency
Notes
Audio core
343/250/200 MHz/100/
50 MHz/2x Osc/Osc
50 MHz/2x Osc/Osc
Audio input clock trunk. CCU drives
one of several frequencies as noted.
one of several frequencies as noted.
DMA 0
50/OSC
DMA clock
DMA1
50/OSC
DMA clock
Audio fabric clock
50/OSC
Fabric clock derived from audio core
clock
clock