Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
Low Power Engine (LPE) for Audio (I
2
S)
706
Datasheet
Note:
The M/N divider has bypass option so VLV could be configured to act same as TNG.
The LPE M/N divider is designed to produce a clock signal for the SSP block used in
master mode. The divider is based on a generic NOM/DENOM divider. The supplied
Master clock is 25 MHz (XTAL) or 19.2 MHz (LPPLL), but usually be used by the 25 MHz
clock.
master mode. The divider is based on a generic NOM/DENOM divider. The supplied
Master clock is 25 MHz (XTAL) or 19.2 MHz (LPPLL), but usually be used by the 25 MHz
clock.
This mechanism is good for a wide spectrum of generated clocks. Two registers must be
configured to get the target SSP clock. The values for the Nominator and Denominator
registers are the smallest divider of:
configured to get the target SSP clock. The values for the Nominator and Denominator
registers are the smallest divider of:
16.5.5.1
Example
If we want to generate 17.64 MHz (=400x44.1 KHz) output clock out of 25 MHz clock,
we need to program “NOM = 441” and “DENOM = 625”:
we need to program “NOM = 441” and “DENOM = 625”:
17.64 MHz = (441/625) x 25 MHz
In general the M over N can generate fractional devisor that could be used for
generating the required clocks for Audio codec.
generating the required clocks for Audio codec.
describes some configuration
options of this generic divider:
Figure 23. SSP CCLK Structure
SSP0
M/N
XOSC = 25MHz
/ PLL = 19.2MHz
CFG REG
SSP1
M/N
CFG REG
SSP2
M/N
CFG REG
SSP2 CCLK
SSP1 CCLK
SSP0 CCLK
Nominator
Denominator
=
Source_clock
Target_clock