Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
Datasheet
707
Low Power Engine (LPE) for Audio (I
2
S)
16.5.5.2
Accuracy and Jitter
The output of the M/N is equal to the desired clock in average with Jitter of 20nTXE for
25 MHz input clock.
25 MHz input clock.
16.5.5.3
Configuration
Following configurable fields per M/N divider/SSP are in LPE shim registers:
16.6
SSP (I
2
S)
The processor audio subsystem consists of the LPE Audio Engine and three
Synchronous Serial Protocol (SSP) ports. These ports are used in PCM mode and enable
simultaneous support of voice and audio streams over I
Synchronous Serial Protocol (SSP) ports. These ports are used in PCM mode and enable
simultaneous support of voice and audio streams over I
2
S. The processor audio
subsystem also includes two DMA controllers dedicated to the LPE. The LPE DMA
controllers are used for transferring data between external memory and CCMs,
between CCMs and the SSP ports, and between CCMs. All peripheral ports can operate
simultaneously.
controllers are used for transferring data between external memory and CCMs,
between CCMs and the SSP ports, and between CCMs. All peripheral ports can operate
simultaneously.
16.6.1
Introduction
The Enhanced SSP Serial Ports are full-duplex synchronous serial interfaces. They can
connect to a variety of external analog-to-digital (A/D) converters, audio, and
telecommunication codecs, and many other devices which use serial protocols for
connect to a variety of external analog-to-digital (A/D) converters, audio, and
telecommunication codecs, and many other devices which use serial protocols for
Table 127. M/N Values, Examples
Source Clock
Frequency
Requested Clock
M/N Value
25 MHz
48 KHz
6/3125
48K x 24 = 1.152 MHz
1152/25000
48K x32 = 1.536 MHz
1536/25000
48K x 64 = 3.072 MHz
3072/25000
44.1 KHz
441/250000
48K x 400 = 19.2 MHz
96/125
44.1K x 400 = 17.64 MHz
441/625
Table 128. M/N Configurable Fields
Field
Width
Description
Bypass
1 bit
When set M/N divider is bypass. Clock from CCU is connected directly to
SSP CCLK
SSP CCLK
EN
1 bit
Enable the divider
Update
1 bit
Update divider parameters
M Value
20 bits
Nominator value
N Value
20 bits
Denominator value