Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
Low Power Engine (LPE) for Audio (I
2
S)
710
Datasheet
16.6.5
Supported Formats
The SSP consists of four pins that are used to transfer data between the processor and
external Audio codecs, modems, or other peripherals. Although four serial-data formats
exist, each has the same basic structure, and in all cases the following pins are used in
the following manner:
external Audio codecs, modems, or other peripherals. Although four serial-data formats
exist, each has the same basic structure, and in all cases the following pins are used in
the following manner:
•
I2Sx_CLK—Defines the bit rate at which serial data is driven onto and sampled
from the port
from the port
•
I2Sx_FRM—Defines the boundaries of a basic data “unit,” comprised of multiple
serial bits
serial bits
•
I2Sx_DATAIN—The serial data path for transmitted data, from system to peripheral
•
I2Sx_DATAOUT—The serial data path for received data, from peripheral to system
A data frame can contain from 4 to 32 bits, depending on the selected format. Serial
data is transmitted most significant bit first. The Programmable Serial Protocol (PSP)
format is used to implement I
data is transmitted most significant bit first. The Programmable Serial Protocol (PSP)
format is used to implement I
2
S.
Master and Slave modes are supported. When driven by the Enhanced SSP, the
I2Sx_CLK only toggles during active transfers (not continuously) unless ECRA/ECRB
functions are used. When the I2Sx_CLK is driven by another device, it is allowed to be
either continuous or only driven during transfers, but certain restrictions on PSP
parameters apply.
I2Sx_CLK only toggles during active transfers (not continuously) unless ECRA/ECRB
functions are used. When the I2Sx_CLK is driven by another device, it is allowed to be
either continuous or only driven during transfers, but certain restrictions on PSP
parameters apply.
Normally, the serial clock (I2Sx_CLK), if driven by the Enhanced SSP Port, only toggles
while an active data transfer is underway. There are several conditions, however, that
may cause the clock to run continuously. If the Receive With Out Transmit mode is
enabled by setting the SSCR1.RWOT bit to 1, the I2Sx_CLK will toggle regardless of
whether Transmit data exists within the Transmit FIFO. The I2Sx_CLK will also toggle
continuously if the Enhanced SSP is in Network mode, or if ECRA, or ECRB is enabled.
At other times, I2Sx_CLK will be held in an inactiveI2Sx_FRM or idle state, as defined
by the specified protocol under which it operates.
while an active data transfer is underway. There are several conditions, however, that
may cause the clock to run continuously. If the Receive With Out Transmit mode is
enabled by setting the SSCR1.RWOT bit to 1, the I2Sx_CLK will toggle regardless of
whether Transmit data exists within the Transmit FIFO. The I2Sx_CLK will also toggle
continuously if the Enhanced SSP is in Network mode, or if ECRA, or ECRB is enabled.
At other times, I2Sx_CLK will be held in an inactiveI2Sx_FRM or idle state, as defined
by the specified protocol under which it operates.
16.6.5.1
Programmable Serial Protocol (PSP)
There are many variations of the frame behavior for different codecs and protocol
formats. To allow flexibility the PSP format allows I2Sx_FRM to be programmable in
direction, delay, polarity, and width. Master and Slave modes are supported. PSP can
be programmed to be either full or half duplex.
formats. To allow flexibility the PSP format allows I2Sx_FRM to be programmable in
direction, delay, polarity, and width. Master and Slave modes are supported. PSP can
be programmed to be either full or half duplex.
The I2Sx_CLK function behavior varies between each format. PSP lets programmers
choose which edge of I2Sx_CLK to use for switching Transmit data, and for sampling
Receive data. In addition, programmers can control the idle state for I2Sx_CLK and the
number of active clocks that precede and follow the data transmission.
choose which edge of I2Sx_CLK to use for switching Transmit data, and for sampling
Receive data. In addition, programmers can control the idle state for I2Sx_CLK and the
number of active clocks that precede and follow the data transmission.
The PSP format provides programmability for several parameters that determine the
transfer timings between data samples. There are four possible serial clock sub-modes,
depending on the I2Sx_CLK edges selected for driving data and sampling received
data, and the selection of idle state of the clock.
transfer timings between data samples. There are four possible serial clock sub-modes,
depending on the I2Sx_CLK edges selected for driving data and sampling received
data, and the selection of idle state of the clock.