Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
Low Power Engine (LPE) for Audio (I
2
S)
712
Datasheet
Note:
The I2Sx_FRM Delay must not extend beyond the end of T4. I2Sx_FRM Width must be
asserted for at least 1 I2Sx_CLK, and should be de-asserted before the end of the T4
cycle (for example, in terms of time, not bit values, (T5 + T6) <= (T1 + T2 + T3 + T4),
asserted for at least 1 I2Sx_CLK, and should be de-asserted before the end of the T4
cycle (for example, in terms of time, not bit values, (T5 + T6) <= (T1 + T2 + T3 + T4),
Figure 25. Programmable Serial Protocol Format (Consecutive Transfers)
Table 129. Programmable Protocol Parameters
Symbol
Definition
(Register.Bit Field)
Range
Units
Serial Clock Mode
(SSPSP.SCMODE)
(Drive, Sample, I2Sx_CLK
Idle)
0 = Fall, Rise, Low
1 = Rise, Fall, Low
1 = Rise, Fall, Low
2 = Rise, Fall, High
3 = Fall, Rise, High
3 = Fall, Rise, High
Serial Frame Polarity
(SSPSP.SFRMP)
High or Low
T1
Start Delay
(SSPSP.STRTDLY)
0–7
Clock Period
T2
Dummy Start
(SSPSP.DMYSTRT)
0–3
Clock Period
T3
Data Size
(SSCRO.EDSS AND SSCRO.DSS)
4–32
Clock Period
T4
Dummy Stop
(SSPSP.DMYSTOP)
0–3
Clock Period
T5
I2Sx_FRM Delay
(SPSP.SFRMDLY)
0–88
Half Clock
Period
T6
I2Sx_FRM Width
(SSPSP.SFRMWDTH)
1–44
Clock Period
End of Transfer Data State
(SSPSP.ETDS)
Low or [bit 0]
SSPSP.SCMODE
I2Sx_DATAOUT
I2Sx_FRM
I2Sx_CLK
00
01
10
11
I2Sx_DATAOUT
SSPSP.SFRMP=1
SSPSP.SFRMP=0
MSB
LSB
MSB
LSB
MSB
MSB
LSB
LSB
T1
T1
T2
T3
T4
T4
T3
T2
T5
T6
T5
T6
End of Transfer
Data State
End of Transfer
Data State