Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
Datasheet
713
Low Power Engine (LPE) for Audio (I
2
S)
1<= T6 < (T2 + T3 + T4), and (T5 + T6) >= (T1 + 1) to ensure that I2Sx_FRM is
asserted for at least 2 edges of the I2Sx_CLK). The T1 Start Delay value should be
programmed to 0 when the I2Sx_CLK is enabled by either of the SSCR1.ECRA or
SSCR1.ECRB bits. While the PSP can be programmed to generate the assertion of
I2Sx_FRM during the middle of the data transfer (after the MSB was sent), the
Enhanced SSP will not be able to receive data in Frame slave mode (SSCR1SFRMDIR =
1) if the assertion of Frame is not before the MSB is sent (that is, T5 T2 if
SSCR1.SFRMDIR =1). Transmit Data will transition from the “End of Transfer Data
State” to the next MSB value upon the assertion of Frame. The Start Delay field should
be programmed to 0 whenever I2Sx_CLK or I2Sx_FRM is configured as an input. Clock
state is not defined between two active frame periods. Clock can be active or inactive
between two active frame periods.
asserted for at least 2 edges of the I2Sx_CLK). The T1 Start Delay value should be
programmed to 0 when the I2Sx_CLK is enabled by either of the SSCR1.ECRA or
SSCR1.ECRB bits. While the PSP can be programmed to generate the assertion of
I2Sx_FRM during the middle of the data transfer (after the MSB was sent), the
Enhanced SSP will not be able to receive data in Frame slave mode (SSCR1SFRMDIR =
1) if the assertion of Frame is not before the MSB is sent (that is, T5 T2 if
SSCR1.SFRMDIR =1). Transmit Data will transition from the “End of Transfer Data
State” to the next MSB value upon the assertion of Frame. The Start Delay field should
be programmed to 0 whenever I2Sx_CLK or I2Sx_FRM is configured as an input. Clock
state is not defined between two active frame periods. Clock can be active or inactive
between two active frame periods.
16.7
Programming Model
The CPU or DMA access data through the Enhanced SSP Port’s Transmit and Receive
FIFOs. A CPU access takes the form of programmed I/O, transferring one FIFO entry
per access. CPU accesses would normally be triggered off of an SSSR Interrupt and
must always be 32 bits wide. The CPU Writes to the FIFOs are 32 bits wide, but the
serializing logic will ignore all bits beyond the programmed FIFO data size (EDSS/DSS
value). CPU Reads to the FIFOs are also 32 bits wide, but the Receive data written into
the RX FIFO (from the RXD line) is stored with zeroes in the MSBs down to the
programmed data size. The FIFOs can also be accessed by DMA bursts, which must be
in multiples of 1, 2, or 4 bytes, depending upon the EDSS value, and must also transfer
one FIFO entry per access. When the SSCR0.EDSS bit is set, DMA bursts must be in
multiples of 4 bytes (the DMA must have the Enhanced SSP configured as a 32-bit
peripheral). The DMA DCMD.width register must be at least the SSP data size
programmed into the SSP control registers EDSS and DSS. The FIFO is seen as one 32-
bit location by the processor. For Writes, the Enhanced SSP port takes the data from
the Transmit FIFO, serializes it, and sends it over the serial wire (I2Sx_DATAOUT) to
the external peripheral. Receive data from the external peripheral (on I2Sx_DATAIN) is
converted to parallel words and stored in the Receive FIFO.
FIFOs. A CPU access takes the form of programmed I/O, transferring one FIFO entry
per access. CPU accesses would normally be triggered off of an SSSR Interrupt and
must always be 32 bits wide. The CPU Writes to the FIFOs are 32 bits wide, but the
serializing logic will ignore all bits beyond the programmed FIFO data size (EDSS/DSS
value). CPU Reads to the FIFOs are also 32 bits wide, but the Receive data written into
the RX FIFO (from the RXD line) is stored with zeroes in the MSBs down to the
programmed data size. The FIFOs can also be accessed by DMA bursts, which must be
in multiples of 1, 2, or 4 bytes, depending upon the EDSS value, and must also transfer
one FIFO entry per access. When the SSCR0.EDSS bit is set, DMA bursts must be in
multiples of 4 bytes (the DMA must have the Enhanced SSP configured as a 32-bit
peripheral). The DMA DCMD.width register must be at least the SSP data size
programmed into the SSP control registers EDSS and DSS. The FIFO is seen as one 32-
bit location by the processor. For Writes, the Enhanced SSP port takes the data from
the Transmit FIFO, serializes it, and sends it over the serial wire (I2Sx_DATAOUT) to
the external peripheral. Receive data from the external peripheral (on I2Sx_DATAIN) is
converted to parallel words and stored in the Receive FIFO.
A programmable FIFO trigger threshold, when exceeded, generates an Interrupt or
DMA service request that, if enabled, signals the IA-32 CPU or DMA respectively to
empty the Receive FIFO or to refill the Transmit FIFO. The Transmit and Receive FIFOs
are differentiated by whether the access is a Read or a Write transfer. Reads
automatically target the Receive FIFO, while Writes will write data to the Transmit FIFO.
From a memory-map perspective, they are at the same address. Each read or write is 1
SSP sample.
DMA service request that, if enabled, signals the IA-32 CPU or DMA respectively to
empty the Receive FIFO or to refill the Transmit FIFO. The Transmit and Receive FIFOs
are differentiated by whether the access is a Read or a Write transfer. Reads
automatically target the Receive FIFO, while Writes will write data to the Transmit FIFO.
From a memory-map perspective, they are at the same address. Each read or write is 1
SSP sample.
16.7.1
PIO and DMA Programming Considerations
All CPU and DMA accesses transfer one FIFO entry per access. Data in the FIFOs is
always stored with one 32-bit value per data sample, regardless of the format data
word length. Within each 32-bit field, the stored data sample is right-justified, with the
least significant bit of the word in bit 0. In the Receive FIFO, unused bits are packed as
zeroes above the most significant bit. In the Transmit FIFO, unused don’t-care bits are
always stored with one 32-bit value per data sample, regardless of the format data
word length. Within each 32-bit field, the stored data sample is right-justified, with the
least significant bit of the word in bit 0. In the Receive FIFO, unused bits are packed as
zeroes above the most significant bit. In the Transmit FIFO, unused don’t-care bits are