Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
PCI Express* 2.0
720
Datasheet
18
PCI Express* 2.0
There are four lanes and up to four PCI Express root ports, each supporting the PCI
Express* Base Specification, Rev. 2.0 at a maximum 5 GT/s signaling rate. The root
ports can be configured to support a diverse set of lane assignments.
Express* Base Specification, Rev. 2.0 at a maximum 5 GT/s signaling rate. The root
ports can be configured to support a diverse set of lane assignments.
18.1
Signal Descriptions
See
for additional details.
The signal description table has the following headings:
•
Signal Name: The name of the signal/pin
•
Direction: The buffer direction can be either input, output, or I/O (bidirectional)
•
Type: The buffer type found in
•
Description: A brief explanation of the signal’s function
Note:
PMC_WAKE_PCIE[3:0]# are not listed, but can be used by PCI Express* devices.
Please see
Please see
details.
IO
IO
IO
IO
PCI Express* 2.0
RP 1
RP 2
RP 3
RP 4
Lane 0 Lane 1 Lane 2 Lane 3