Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
Datasheet
721
PCI Express* 2.0
18.2
Features
•
Conforms to PCI Express* Base Specification, Rev. 2.0
•
5.0 or 2.5 GT/s operation per root port
•
Virtual Channel support for VC0
•
x1, x2 and x4 link widths (auto negotiated)
•
Flexible Root Port (1-4) configuration options
— (4) x1’s
— (2) x2’s
— (1) x2 plus (2) x1’s
— (1) x4
•
Interrupts and Events
— Legacy (INTx) and MSI Interrupts
— General Purpose Events
Table 130. Signals
Signal Name
Direction/
Type
Description
PCIE_TXP[3:0]
PCIE_TXN[3:0]
O
PCIe
PCI Express* Transmit
PCI Express* Ports 3:0 transmit pair (P and N) signals. Each pair
PCI Express* Ports 3:0 transmit pair (P and N) signals. Each pair
makes up the transmit half of a lane.
PCIE_RXP[3:0]
PCIE_RXN[3:0]
I
PCIe
PCI Express* Receive:
PCI Express* Ports 3:0 receive pair (P and N) signals. Each pair
PCI Express* Ports 3:0 receive pair (P and N) signals. Each pair
makes up the receive half of lane.
PCIE_CLKP[3:0]
PCIE_CLKN[3:0]
O
PCIe
PCI Express* Output Clock
100-MHz differential clock signals.
100-MHz differential clock signals.
PCIE_CLKREQ[3:0]#
I
CMOS_1P8
PCI Express* Clock Request
Used for devices that need to request one of the four output
Used for devices that need to request one of the four output
clocks. Each clock request maps to the matching clock output
(e.g., PCI_CLKREQ[0] maps to PCIE_CLKP/N[0]).
These signals are muxed and may be used by other functions.
These signals are muxed and may be used by other functions.
PCIE_RCOMP_P
PCIE_RCOMP_N
PCIE_RCOMP_N
I/O
These pins are used to connect the external resistors used for
Rcomp.
Figure 27. PCIe* 2.0 Lane 0 Signal Example
T
X
P
[0]
R
E
Q
[0]
T
X
N
[0]
R
X
P
[0]
R
X
N
[0]
C
L
K
P
[0]
C
L
K
N
[0]
Lane 0