Intel N2820 FH8065301616603 Data Sheet
Product codes
FH8065301616603
Electrical Specifications
80
Datasheet
8.2.1
Post Board-Attach
The storage condition limits for the component once attached to the application board
are not specified. Intel does not conduct component-level certification assessments
post board-attach given the multitude of attach methods, socket types, and board
types used by customers.
are not specified. Intel does not conduct component-level certification assessments
post board-attach given the multitude of attach methods, socket types, and board
types used by customers.
Provided as general guidance only, board-level Intel-branded products are specified
and certified to meet the following temperature and humidity limits:
and certified to meet the following temperature and humidity limits:
•
Non-Operating Temperature Limit: -40 °C to 70 °C
•
Humidity: 50% to 90%, non-condensing with a maximum wet-bulb of 28 °C
8.3
Voltage and Current Specifications
The I/O buffer supply voltages are specified at the processor package balls. The
tolerances shown in the following table are inclusive of all noise from DC up to 20 MHz.
The voltage rails should be measured with a bandwidth limited oscilloscope with a roll-
off of 3 dB/decade above 20 MHz under all operating conditions.
tolerances shown in the following table are inclusive of all noise from DC up to 20 MHz.
The voltage rails should be measured with a bandwidth limited oscilloscope with a roll-
off of 3 dB/decade above 20 MHz under all operating conditions.
indicates
which supplies are connected directly to a voltage regulator or to a filtered voltage rail.
For voltage rails that are connected to a filter, they should be measured at the input of
the filter. If the recommended platform decoupling guidelines cannot be met, the
system designer will have to make trade-offs between the voltage regulator out DC
tolerance and the decoupling performances of the capacitor network to stay within the
voltage tolerances listed below.
For voltage rails that are connected to a filter, they should be measured at the input of
the filter. If the recommended platform decoupling guidelines cannot be met, the
system designer will have to make trade-offs between the voltage regulator out DC
tolerance and the decoupling performances of the capacitor network to stay within the
voltage tolerances listed below.
Note:
The SoC is a pre-launch product. Voltage and current specifications are subject to
change.
change.
Platform Rail
Voltage
Tolerances
Max Icc
-M
(2.xW SDP)
Max Icc
-M
Max Icc
-D
V1P0A
- UNCORE_V1P0_G3
- USB3_V1P0_G3
- UNCORE_V1P0_G3
- USB3_V1P0_G3
1.0 V
DC: ±2%
AC: ±3%
325 mA
325 mA
350 mA
V1P24A
- USB_HSIC_V1P24_G3
(Can connect to V1P0A when USB
- USB_HSIC_V1P24_G3
(Can connect to V1P0A when USB
HSIC isn’t used)
1.24 V
DC: ±3%
AC: ±2%
35 mA
35 mA
35 mA
V1P8A
- PCU_V1P8_G3
- PMC_V1P8_G3
- UNCORE_V1P8_G3
- USB_V1P8_G3
- USB_ULPI_V1P8_G3
- PCU_V1P8_G3
- PMC_V1P8_G3
- UNCORE_V1P8_G3
- USB_V1P8_G3
- USB_ULPI_V1P8_G3
1.8 V
DC: ±3%
AC: ±2%
65 mA
65 mA
65 mA
V3P3A
- PCU_V3P3_G3
- USB_V3P3_G3
- PCU_V3P3_G3
- USB_V3P3_G3
3.3 V
DC: ±2%
AC: ±3%
50 mA
50 mA
55 mA