Intel Atom Processor N270 AU80586GE025D Data Sheet
Product codes
AU80586GE025D
Introduction
Datasheet
7
1.2
Terminology
Term Definition
#
A “#” symbol after a signal name refers to an active low signal, indicating
a signal is in the active state when driven to a low level. For example,
when RESET# is low, a reset has been requested. Conversely, when NMI
is high, a non-maskable interrupt has occurred. In the case of signals
where the name does not imply an active state but describes part of a
binary sequence (such as address or data), the “#” symbol implies that
the signal is inverted. For example, D [3:0] = “HLHL” refers to a hex ‘A’,
and D [3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L=
Low logic level).
a signal is in the active state when driven to a low level. For example,
when RESET# is low, a reset has been requested. Conversely, when NMI
is high, a non-maskable interrupt has occurred. In the case of signals
where the name does not imply an active state but describes part of a
binary sequence (such as address or data), the “#” symbol implies that
the signal is inverted. For example, D [3:0] = “HLHL” refers to a hex ‘A’,
and D [3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L=
Low logic level).
Front Side Bus
(FSB)
(FSB)
Refers to the interface between the processor and system core logic (also
known as the GMCH chipset components).
known as the GMCH chipset components).
AGTL+
Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+
signaling technology on some Intel processors.
signaling technology on some Intel processors.
CMOS Complementary
metal-Oxide semiconductor.
Storage
Conditions
Conditions
Refers to a non-operational state. The processor may be installed in a
platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor landings should not
be connected to any supply voltages, have any I/Os biased, or receive any
clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device
removed from packaging material) the processor must be handled in
accordance with moisture sensitivity labeling (MSL) as indicated on the
packaging material.
platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor landings should not
be connected to any supply voltages, have any I/Os biased, or receive any
clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device
removed from packaging material) the processor must be handled in
accordance with moisture sensitivity labeling (MSL) as indicated on the
packaging material.
Enhanced Intel
SpeedStep®
Technology
SpeedStep®
Technology
Technology that provides power management capabilities to low power
devices.
devices.
Processor Core
Processor core die with integrated L1 and L2 cache. All AC timing and
signal integrity specifications are at the pads of the processor core.
signal integrity specifications are at the pads of the processor core.
TDP
Thermal Design Power
V
CC
The processor core power supply
VR Voltage
Regulator
V
SS
The processor ground
V
CC
HFM V
CC
at Highest Frequency Mode (HFM).
V
CC
LFM V
CC
at Lowest Frequency Mode (LFM).