Data Sheet (AU80586GE025D)Table of ContentsContents3Figures4Tables4Revision History51 Introduction61.1 Major Features61.2 Terminology71.3 References92 Low Power Features102.1 Clock Control and Low-power States102.1.1 Thread Low-power State Descriptions122.1.1.1 Thread C0 State122.1.1.2 Thread C1/AutoHALT Power-down State122.1.1.3 Thread C1/MWAIT Power-down State132.1.1.4 Thread C2 State132.1.1.5 Thread C4 State132.1.2 Package Low-power State Descriptions132.1.2.1 Normal State132.1.2.2 Stop-Grant State132.1.2.3 Stop-Grant Snoop State142.1.2.4 Sleep State142.1.2.5 Deep Sleep State152.1.2.6 Deeper Sleep State152.1.2.6.1 Intel Enhanced Deeper Sleep State152.2 Dynamic Cache Sizing162.3 Enhanced Intel SpeedStep® Technology172.4 Enhanced Low-Power States182.5 FSB Low Power Enhancements192.5.1 Front Side Bus193 Electrical Specifications203.1 Power and Ground Pins203.2 FSB Clock (BCLK [1:0]) and Processor Clocking203.3 Voltage Identification203.4 Catastrophic Thermal Protection233.5 Reserved and Unused Pins233.6 FSB Frequency Select Signals (BSEL [2:0])233.7 FSB Signal Groups243.8 CMOS Asynchronous Signals253.9 Maximum Ratings253.10 Processor DC Specifications264 Package Mechanical Specifications and Pin Information334.1 Package Mechanical Specifications334.1.1 Package Mechanical Drawings344.2 Processor Pin-out Assignment344.3 Signal Description415 Thermal Specifications and Design Considerations505.1 Thermal Diode515.2 Intel® Thermal Monitor535.3 Digital Thermal Sensor555.3.1 Out of Specification Detection565.3.2 PROCHOT# Signal Pin56Size: 547 KBPages: 57Language: EnglishOpen manual