SimpleTech ZeusIOPS User Manual
Zeus
IOPS
3.5-Inch Fibre Channel Solid State Drive Product Manual Rev. 1.0
29
G
ROUNDING
Signal and chassis ground are not connected together in the drive. To ensure minimal EM emissions,
the user should provide maximum surface contact area when connecting the drive to chassis ground.
the user should provide maximum surface contact area when connecting the drive to chassis ground.
F
AULT
LED O
UT
S
IGNAL
The Fault LED Out signal is driven by an open collector driver capable of sinking 30mA. It is driven
low when an internal fault is detected along with both Enable Bypass signals.
low when an internal fault is detected along with both Enable Bypass signals.
R
EADY
LED O
UT
S
IGNAL
The Ready LED Out signal is driven by an open collector driver capable of sinking 30mA. It will
typically be connected to the cathode of an LED in the enclosure. The Ready LED function is nearly
identical to the SFF-8045 specification for hot-plugging implementations; however, since the drive
has no motor, it behaves as follows:
typically be connected to the cathode of an LED in the enclosure. The Ready LED function is nearly
identical to the SFF-8045 specification for hot-plugging implementations; however, since the drive
has no motor, it behaves as follows:
•
Drive not mated:
The signal is de-asserted (i.e., High). The LED is off.
The signal is de-asserted (i.e., High). The LED is off.
•
Drive mated, power-up diagnostics in progress:
The signal is asserted for 1/3 of a second and de-asserted for 2/3 of a second. This
represents a 1Hz Short flash.
The signal is asserted for 1/3 of a second and de-asserted for 2/3 of a second. This
represents a 1Hz Short flash.
•
Drive mated, firmware running, drive in progress of becoming ready:
The signal is asserted for one-half second and de-asserted for one-half second. This
represents a 1Hz Normal flash.
The signal is asserted for one-half second and de-asserted for one-half second. This
represents a 1Hz Normal flash.
•
Drive mated, firmware running and drive ready:
The signal is asserted when either of the loops is brought up. The signal will de-assert when
the drive is active on either of the fibre loops.
The signal is asserted when either of the loops is brought up. The signal will de-assert when
the drive is active on either of the fibre loops.
-P
ARALLEL
ESI
AND
SEL_n/P_ESI_n
SEL_n/P_ESI_n are a set of dual purpose pins that are used to convey either a Loop Identifier
address or Enclosure Service Information (where this is supported by the backplane) to the SSD.
address or Enclosure Service Information (where this is supported by the backplane) to the SSD.
-Parallel ESI determines the function of Sel_n/-P_ESI_n. It is a TTL open-drain output from the SSD.
When -Parallel ESI is de-asserted (high), the backplane must present SEL_ID information on SEL_n/
P_ESI_n. See SEL_ID Function.
P_ESI_n. See SEL_ID Function.
When -Parallel ESI is asserted (low), the backplane must present Enclosure Service Information (if
supported) on SEL_n/P_ESI_n. See SEL_ID Function on page 16.
supported) on SEL_n/P_ESI_n. See SEL_ID Function on page 16.
Note: The maximum response time to a change in state of -Parallel ESI is 1
μS.