Renesas M32R-FPU User Manual

APPENDICES

APPENDICES-8

M32R-FPU Software Manual (Rev.1.01)

Appendix 3  Pipeline Processing

Appendix 3.1   Instructions and Pipeline Processing

Appendix Figure 3.1.1 shows each instruction type and the pipeline process.

APPENDIX 3

Appendix 3 Pipeline Processing

IF

D

E

MEM2

MEM1

WB

Pipeline Stage

Pipeline Stage

Pipeline Stage

■

 Load/Store instruction

*The number of cycles required by the MEM1 stage varies according to the access, 
  but the MEM2 stage is normally executed in 1 cycle.

IF

D

E

WB

■

 All other integer instructions

*Multi-cycle instructions such as the multiply instruction are executed in multiple 
  cycles in the E stage.

IF

D

E

WB

E

6 stages

IF

D

EM

E2

EA

WB

Pipeline Stage

■

 FPU instruction (FMADD, FMSUB)

* The EM and EA stages cannot be executed at the same time as the E or E1 stage.

6 stages

IF

D

E1

E2

WB

Pipeline Stage

  

 FPU instruction (excluding FMADD, FMSUB)

*The E1 and E2 stages cannot be executed at the same time as the E stage.
*The E1 stage of the FDIV instruction requires 14 cycles.

5 stages

4 stages

*Operation stages with the same name cannot be executed at the same time. In general, stages with
  different names can be executed in parallel, but the following combinations are not acceptable.
 

¥ E stage executed with E1, E2, EM or EA stage.

 

¥ E1 stage executed with EM or EA stage.

*Bypass process: When using the result of one instruction in a subsequent instruction, the first result 
  may bypass the register file and be sent on to the execution stage of the subsequent instruction.
  The following is an example of a bypass process:

¥ E stage continuing to WB stage 

→

 E, E1, EM stages

¥ MEM2 stage continuing to WB stage 

→

 E, E1, EM, EA stages

Appendix Figure 3.1.1 Instructions and Pipeline Process