Renesas M32R-FPU User Manual

APPENDICES

APPENDICES-10

M32R-FPU Software Manual (Rev.1.01)

Appendix Figure 3.2.1 Pipeline Flow with no Stall (1)

Appendix 3.2   Pipeline Basic Operation

(1) Pipeline Flow with no Stall

The following diagram shows an ideal pipeline flow that has no stall and executes each

instruction in 1 clock cycle. (Since this is just an ideal case, all instructions may not be

piplined in.)

APPENDIX 3

Appendix 3 Pipeline Processing

<Case 1>  Integer instructions (register-to-register) are executed continuously

IF

D

E

WB

IF

D

WB

E

D

WB

E

IF

D

WB

E

<Case 2>  Load/store instructions to destination are accessed in 1 cycle continuously

IF

D

E

WB

IF

D

WB

MEM2

MEM1 MEM2

E

MEM1

IF

D

E

WB

IF

D

WB

MEM2

MEM1 MEM2

E

MEM1

IF

D

E

WB

IF

D

WB

MEM1 MEM1 MEM2

E

IF

D

E

WB

IF

D

WB

E

<Case 3>  Register-register instructions are executed with no register dependency following 

a load/store instruction (out-of-order-completion)

IF

* A multi-cycle instruction, such as multiply or divide, executes 
  multiple cycles in the E stage.

* A multi-cycle instruction, such as multiply or divide, executes multiple 
  cycles in the E stage.