Philips 8-bit microcontroller with two-clock 80C51 core UM10109 User Manual

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© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual
Rev. 02 — 23 May 2005 
107 of 133
Philips Semiconductors
UM10109
P89LPC932A1 User manual
 
Note that if DEEDAT is written prior to a write to DEEADR (if DEECON[5:4] = ‘00’), a Data 
EEPROM write operation will commence. The user must take caution that such cases do 
not occur during a read. An example is if the Data EEPROM is read in an interrupt service 
routine with the interrupt occurring in the middle of a Data EEPROM cycle. The user 
should disable interrupts during a Data EEPROM write operation (see 
).
17.2 Data EEPROM write
A byte can be written via polling or interrupt:
1. Write to DEECON with ECTL1/ECTL0 (DEECON[5:4]) = ‘00’ and correct bit 8 address 
to EADR8. (Note that if the correct values are already written to DEECON, there is no 
need to write to this register.)
2. Write the data to the DEEDAT register.
3. Write address bits 7 to 0 to DEEADR.
4. If both the EIEE (IEN1.7) bit and the EA (IEN0.7) bit are logic 1s, wait for the Data 
EEPROM interrupt then read/poll the EEIF (DEECON.7) bit until it is set to logic 1. If 
EIEE or EA is logic 0, the interrupt is disabled and only polling is enabled. When EEIF 
is logic 1, the operation is complete and data is written.
As a write to the DEEDAT register followed by a write to the DEEADR register will 
automatically set off a write (if DEECON[5:4] = ‘00’), the user must take great caution in a 
write to the DEEDAT register. It is strongly recommended that the user disables interrupts 
prior to a write to the DEEDAT register and enable interrupts after all writes are over. An 
example is as follows:
CLR EA
;disable interrupt
MOV DEEDAT,@R0  ;write data pattern
MOV DEEADR,@R1  ;write address for the data
SETB  EA
;wait for the interrupt orpoll the DEECON.7 (EEIF) bit
17.3 Hardware reset
During any hardware reset, including watchdog and system timer reset, the state machine 
that ‘remembers’ a write to the DEEDAT register will be initialized. If a write to the 
DEEDAT register occurs followed by a hardware reset, a write to the DEEADR register 
without a prior write to the DEEDAT register will result in a read cycle.
17.4 Multiple writes to the DEEDAT register
If there are multiple writes to the DEEDAT register before a write to the DEEADR register, 
the last data written to the DEEDAT register will be written to the corresponding address.
17.5 Sequences of writes to DEECON and DEEDAT registers
A write to the DEEDAT register is considered a valid write (i.e, will trigger the state 
machine to ‘remember’ a write operation is to commence) if DEECON[5:4] = ‘00’. If these 
mode bits are already ‘00’ and address bit 8 is correct, there is no need to write to the 
DEECON register prior to a write to the DEEDAT register.
17.6 Data EEPROM Row Fill
A row (64 bytes) can be filled with a predetermined data pattern via polling or interrupt: