Tektronix Webcam 070-8030-01 User Manual
Theory of Operation
1780R-Series Service Manual
3–45
The Master MPU normally does not use the Non-Maskable Interrupt (NMI)
signal and it is held high by a pull-up voltage from one segment of R360. It can,
however, be asserted for troubleshooting by placing a jumper across J342.
signal and it is held high by a pull-up voltage from one segment of R360. It can,
however, be asserted for troubleshooting by placing a jumper across J342.
Latches. The Master MPU uses a multiplexed data bus and the lower 16 address
bits are latched by external latches U135 and U137. The latches are actuated by
an inverted /ADS signal which latches data during processor cycle T1. These two
latches are normally active, but are tri-stated during Dynamic Memory Access
(DMA) cycles by HOLDA. A series of pull-ups force address bits IA0 through
IA3, IA13 through IA18, and IA23 to a high state during DMA transfers in order
to retrieve readout engine data from the highest part of DRAM.
bits are latched by external latches U135 and U137. The latches are actuated by
an inverted /ADS signal which latches data during processor cycle T1. These two
latches are normally active, but are tri-stated during Dynamic Memory Access
(DMA) cycles by HOLDA. A series of pull-ups force address bits IA0 through
IA3, IA13 through IA18, and IA23 to a high state during DMA transfers in order
to retrieve readout engine data from the highest part of DRAM.
The Master MPU data also goes to a data buffer consisting of U140, U142, and
U145, as well as to the DRAM data bits. This minimizes access time to the
DRAM while maintaining strong bus drive for other peripherals. The three data
buffers automatically swap data as necessary to provide a true 8-bit bus for the
8-bit devices and a 16-bit bus for the Read-Only Memory (ROM) and DRAM. A
ROM or DRAM access will use both halves of the bus through U142 and U145.
An 8-bit device such as the UART will use only data bits 0 through 8 from
U140.
U145, as well as to the DRAM data bits. This minimizes access time to the
DRAM while maintaining strong bus drive for other peripherals. The three data
buffers automatically swap data as necessary to provide a true 8-bit bus for the
8-bit devices and a 16-bit bus for the Read-Only Memory (ROM) and DRAM. A
ROM or DRAM access will use both halves of the bus through U142 and U145.
An 8-bit device such as the UART will use only data bits 0 through 8 from
U140.
Wait State Generator. The data bus buffers and wait states are controlled by U350,
a PAL automatically adding the proper amount of wait states for each type of
device as well as controlling the three data bus buffers. This PAL also generates
the unqualified chip select /LRC that is used by the Line Rate Controller
(Diagram 18).
a PAL automatically adding the proper amount of wait states for each type of
device as well as controlling the three data bus buffers. This PAL also generates
the unqualified chip select /LRC that is used by the Line Rate Controller
(Diagram 18).
Internal Chip Select. The internal chip select PAL U345 creates the bulk of the
chip select enables used by the internal peripherals. U345 also outputs an
inverted /RSTO for the DRAM (Diagram 17).
chip select enables used by the internal peripherals. U345 also outputs an
inverted /RSTO for the DRAM (Diagram 17).
ROM. The ROM consists of two 28-pin chips, U310 and U315. They are
activated whenever a read to the ROM address space is made. A read to ROM
causes /ROMCS to go low along with /RD.
activated whenever a read to the ROM address space is made. A read to ROM
causes /ROMCS to go low along with /RD.
NVRAM. The Non-Volatile RAM, U320, is selected whenever the NVRAM chip
select is addressed for reads or writes. When chip select /NVRAMCS along with
either /WR or /RD is activated, the chip can be written to or read from. Data in
the NVRAM is safe even if instrument mains power is lost.
select is addressed for reads or writes. When chip select /NVRAMCS along with
either /WR or /RD is activated, the chip can be written to or read from. Data in
the NVRAM is safe even if instrument mains power is lost.