Tektronix Webcam 070-8030-01 User Manual
Theory of Operation
1780R-Series Service Manual
3–47
The Master MPU memory access sequence starts when /ADS goes low, forcing
Master MPUGO to be latched high by U595A&B and start the PAL sequence.
/RASO, which is in-line terminated by R361 and becomes /RAS, goes low to
enable the memory chip RAS input. The row addresses must be stable at this
time. 50 ns after /RASO goes low, /COL goes low and switches the address
multiplexers, U353 and U357, from the row to the column addresses. In addition
to switching the address, /COL going low resets the Master MPUGO latch.
Master MPUGO to be latched high by U595A&B and start the PAL sequence.
/RASO, which is in-line terminated by R361 and becomes /RAS, goes low to
enable the memory chip RAS input. The row addresses must be stable at this
time. 50 ns after /RASO goes low, /COL goes low and switches the address
multiplexers, U353 and U357, from the row to the column addresses. In addition
to switching the address, /COL going low resets the Master MPUGO latch.
If the cycle that is starting is destined for the DRAM, one of the two CAS lines
goes low. /LCASO goes low if IA23 is high and IA0 is low and directs the cycle
to the lower DRAM bank. /HCASO goes low when IA23 is high and /HBE goes
low. /RPERW is used to write enable both of the DRAM arrays when it is low;
however, only the bank with its CAS enabled can be written to.
goes low. /LCASO goes low if IA23 is high and IA0 is low and directs the cycle
to the lower DRAM bank. /HCASO goes low when IA23 is high and /HBE goes
low. /RPERW is used to write enable both of the DRAM arrays when it is low;
however, only the bank with its CAS enabled can be written to.
At the start of the next Master MPU cycle, the /RASO line is raised, to allow for
RAS precharge time, and the Master MPU latches data. /LCASO and /HCASO
go high 50 ns after the Master MPU reads the data, to allow hold time while
removing the data before the Master MPU again drives the data bus.
RAS precharge time, and the Master MPU latches data. /LCASO and /HCASO
go high 50 ns after the Master MPU reads the data, to allow hold time while
removing the data before the Master MPU again drives the data bus.
A Direct Memory Access (DMA) cycle is similar to a Master MPU cycle, except
that two extra wait states are added to allow setup time for the D/A Converters.
The Control PAL also does two complete cycles and sends two words to the
readout engine. When control switches from Master MPU to DMA control, the
Master MPU pulls /HOLDA down.
that two extra wait states are added to allow setup time for the D/A Converters.
The Control PAL also does two complete cycles and sends two words to the
readout engine. When control switches from Master MPU to DMA control, the
Master MPU pulls /HOLDA down.
The PAL begins the cycle when /HOLDA and CTTL are both low. CTTL
prevents metastable problems and keeps the PAL aligned with the T states of the
Master MPU. When /HOLDA goes low ROEN/also goes low and signals the
readout engine to place its address on the internal bus lines IA2..IA12. /CYC2 is
also high at this time, signifying that the first of two cycles is beginning.
prevents metastable problems and keeps the PAL aligned with the T states of the
Master MPU. When /HOLDA goes low ROEN/also goes low and signals the
readout engine to place its address on the internal bus lines IA2..IA12. /CYC2 is
also high at this time, signifying that the first of two cycles is beginning.
When the cycle begins, /RASO goes low and starts the DRAM cycle. The
address lines must be stable prior to this point. The /COL line is dropped to
switch from row to column addresses. Both /LCASO and /HCASO go low,
completing the DRAM address sequence and activating the DRAM output
buffers. /PERWR is forced high to ensure a read cycle. The Control PAL LATCH
output goes low and is multiplexed (U457) to output Latch 1.
address lines must be stable prior to this point. The /COL line is dropped to
switch from row to column addresses. Both /LCASO and /HCASO go low,
completing the DRAM address sequence and activating the DRAM output
buffers. /PERWR is forced high to ensure a read cycle. The Control PAL LATCH
output goes low and is multiplexed (U457) to output Latch 1.
At this time the first of two wait states is inserted. No other outputs change
during this period. When the second wait state occurs, /RASO is raised to start
the RAS precharge period. When the first DRAM cycle begins to end, the
LATCH signal goes high, latching data into the first D/A.
during this period. When the second wait state occurs, /RASO is raised to start
the RAS precharge period. When the first DRAM cycle begins to end, the
LATCH signal goes high, latching data into the first D/A.
/LCASO and /HCASO go high to finish the first cycle. The next cycle begins
when /CYC2 goes low and switches address IA1 from 0 to 1, and LATCH1 to
LATCH2.
when /CYC2 goes low and switches address IA1 from 0 to 1, and LATCH1 to
LATCH2.
From this point on, the second cycle is identical to the first cycle. During the
second cycle, the Control PAL enters a special idle state, where /ROEN goes
second cycle, the Control PAL enters a special idle state, where /ROEN goes