Oracle Vacuum Cleaner CPU-56T User Manual

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PCI Bus A
Devices’ Features and Data Paths
SPARC/CPU−56T
77
PCI Bus A
PCI bus A is the primary PCI bus. It runs at 33 MHz and is 32 bit wide. The following
devices are connected to it:
S Ethernet controller
S SCSI controller
S SENTINEL64 PCI−to−PCI bridge
S Universe
Ethernet Controller
The used Ethernet controller is an Intel 82540. It corresponds to Ethernet interface 2
available via the front panel and supports 10/100/1000BaseT Ethernet. Further important
features are:
S Integrated PHY in a small package (uBGA196)
S Compatibility with IEEE 802.3/Ethernet
S DMA capability
S Interrupt generation
SCSI Controller
The used SCSI controller is a LSI53C1010. It supports two dual U2W LVD SCSI buses with
a SCSI data transfer rate of up to 160 MByte/s for each channel. Both SCSI interfaces are
available via the front panel.
a
Two interrupts are generated by the SCSI controller for interrupting the main processor.
a
Both SCSI interfaces have an on−board termination which can be enabled and disabled
via on−board switches. By default, the SCSI termination is enabled.
a
SENTINEL64 PCI−to−PCI Bridge
The SENTINEL64 PCI−To−PCI bridge is used to connect the primary PCI bus A to the
secondary PCI bus B. For details about the SENTINEL64 device refer to the SENTINEL64
Reference Guide available via the Force Computers S.M.A.R.T. server.
a
PCI−to−VME Bridge
The used PCI−To−VME bridge is a Tundra Universe II device. Its main features are:
S Fully compliant to VME64 bus standard