Digi NS9215 User Manual
S E R I A L C O N T R O L M O D U L E : H D L C
HDLC Clock Divider High
432
Hardware Reference NS9215
Register bit
assignment
assignment
Bits
Access
Mnemonic
Reset
Description
D31:08
R
Not used
0
Write this field to 0.
D07
R/W
EN
0
Clock enable
Must be set when the internal clock is used.
Must be set when the internal clock is used.
D06:00
R/W
DIVH
0
Seven MSBs of the divider that generates the HDLC
transmit and receive clock.
transmit and receive clock.