IBM Intel Xeon E5504 46M1078 User Manual

102

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

The FORCE_ODT fields are directly mapped to pins. When the force bits are set, the 
corresponding pin on the interface is always driven high regardless of the cycle that is 
being generated. This register is used in debug only and not during normal operation.

This register contains the ODT activation matrix for RANKS 0 to 3 for Reads.

9

RW

0

MCODT_Writes. Drive MC ODT on reads and writes.

8

RW

0

FORCE_MCODT. Force MC ODT to always be asserted.

7

RW

0

6

RW

0

5

RW

0

FORCE_ODT5. Force ODT pin 5 to always be asserted.

4

RW

0

FORCE_ODT4. Force ODT pin 4 to always be asserted.

3

RW

0

FORCE_ODT3. Force ODT pin 3 to always be asserted.

2

RW

0

FORCE_ODT2. Force ODT pin 2 to always be asserted.

1

RW

0

FORCE_ODT1. Force ODT pin 1 to always be asserted.

0

RW

0

FORCE_ODT0. Force ODT pin 0 to always be asserted.

31:24

RW

1

ODT_RD3. Bit patterns driven out onto ODT pins when Rank3 is read.

23:16

RW

1

ODT_RD2. Bit patterns driven out onto ODT pins when Rank2 is read.

15:8

RW

4

ODT_RD1. Bit patterns driven out onto ODT pins when Rank1 is read.

7:0

RW

4

ODT_RD0. Bit patterns driven out onto ODT pins when Rank0 is read.