IBM Intel Xeon E5504 46M1078 User Manual

104

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

This register contains parameters that specify settings for the Write Address Queue.

These are the parameters used to control parameters within the scheduler.

29:25

RW

6

PRECASWRTHRESHOLD. Threshold above which Medium-Low Priority reads 

cannot PRE-CAS write requests.

24:20

RW

31

PARTWRTHRESHOLD. Threshold used to raise the priority of underfill 

requests in the scheduler. Set to 31 to disable.

19:15

RW

31

ISOCEXITTHRESHOLD. Write Major Mode ISOC Exit Threshold. When the 

number of writes in the WAQ drops below this threshold, the MC will exit write 

major mode in the presence of a read.

14:10

RW

31

ISOCENTRYTHRESHOLD. Write Major Mode ISOC Entry Threshold. When the 

number of writes in the WAQ exceeds this threshold, the MC will enter write 

major mode in the presence of a read.

9:5

RW

22

WMENTRYTHRESHOLD. Write Major Mode Entry Threshold. When the number 

of writes in the WAQ exceeds this threshold, the MC will enter write major 

mode.

4:0

RW

22

WMEXITTHRESHOLD. Write Major Mode Exit Threshold. When the number of 

writes in the WAQ drop below this threshold, the MC will exit write major mode.

12

RW

1

CS_FOR_CKE_TRANSITION. Specifies if chip select is to be asserted when 

CKE transitions with PowerDown entry/exit and SelfRefresh exit.

11

RW

0

FLOAT_EN. When set, the address and command lines will float to save power 

when commands are not being sent out. This setting may not work with 

RDIMMs.

10:6

RW

7

PRECASRDTHRESHOLD. Threshold above which Medium-Low Priority reads 

can PRE-CAS write requests.

5

RW

0

DISABLE_ISOC_RBC_RESERVE. When set this bit will prevent any RBC's 

from being reserved for ISOC.

3

RW

0

ENABLE2N. Enable 2n Timing.

2:0

RW

0

PRIORITYCOUNTER. Upper 3 MSB of 8 bit priority time out counter.