IBM Intel Xeon E5504 46M1078 User Manual

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

55

Mirror Port physical layer control register.

.

Mirror Port Physical Layer Control Register.

.

7

RW

0

SPARE. Spare MiP control register bits.

6

RW

0

DSBL_ENH_MPRX_SYNC. When set, it disables the enhancing 

synchronization scheme for the MiP_Rx.

5

RW

0

MIP_GO_10. When set, the Mip_Tx and Mip_Rx go to L0 directly from 

Config_FlitLock.

4

RW

0

MIP_RX_CRC_SQUASH. When set, replaces CRC errors with CRC special 

packet on MiP Rx.

3

RW

0

MIP_RX_PORT_SEL. Port select for MiP Rx. _PORT_SEL0=QPI Port 0. 

_PORT_SEL1=QPI Port 1.

2

RW

0

MIP_TX_PORT_SEL. Port select for MiP Tx. _PORT_SEL0=QPI Port 0. 

_PORT_SEL1=QPI Port 1.

1

RW

1

MIP_RX_ENABLE. Enables the Rx portion of the mirror port. 

0

RW

1

MIP_TX_ENABLE. Enables the Tx portion of the mirror port.

27

RW

0

LA_LOAD_DISABLE. Disables the loading of the effective values of the 

Intel® QuickPath CSRs when set.

23

RW

0

ENABLE_PRBS. Enables LFSR pattern during bitlock/training.

22

RW

0

ENABLE_SCRAMBLE. Enables data scrambling through LFSR.

14

RW

1

DETERMINISM_MODE. Sets determinism mode of operation.

13

RW

1

DISABLE_AUTO_COMP. Disables automatic entry into compliance.

12

RW

0

INIT_FREEZE. When set, freezes the FSM when initialization aborts.

10:8

RW

0

INIT_MODE. Initialization mode that determines altered initialization 

modes.

7

RW

0

LINK_SPEED. Identifies slow speed or at-speed operation for the Intel QPI 

port.

5

RW

1

PHYINITBEGIN. Instructs the port to start initialization.

4

RW

0

SINGLE_STEP. Enables single step mode.

3

RW

0

LAT_FIX_CTL. If set, instructs the remote agent to fix the latency.

2

RW

0

BYPASS_CALIBRATION. Indicates the physical layer to bypass calibration.