IBM Intel Xeon E5504 46M1078 User Manual
Product codes
46M1078
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
57
Register Description
21:20
RW
0
PAM2_HIENABLE. 0CC000-0CFFFF Attribute (HIENABLE) This field controls
the steering of read and write cycles that address the BIOS area from 0CC000
to 0CFFFF.
00: DRAM Disabled: All accesses are directed to ESI.
01: Read Only: All reads are sent to DRAM. All writes are forwarded to ESI.
10: Write Only: All writes are send to DRAM. Reads are serviced by ESI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
00: DRAM Disabled: All accesses are directed to ESI.
01: Read Only: All reads are sent to DRAM. All writes are forwarded to ESI.
10: Write Only: All writes are send to DRAM. Reads are serviced by ESI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
17:16
RW
0
PAM2_LOENABLE. 0C8000-0CBFFF Attribute (LOENABLE) This field controls
the steering of read and write cycles that address the BIOS area from 0C8000
to 0CBFFF.
00: DRAM Disabled: All accesses are directed to ESI.
01: Read Only: All reads are sent to DRAM. All writes are forwarded to ESI.
10: Write Only: All writes are send to DRAM. Reads are serviced by ESI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
00: DRAM Disabled: All accesses are directed to ESI.
01: Read Only: All reads are sent to DRAM. All writes are forwarded to ESI.
10: Write Only: All writes are send to DRAM. Reads are serviced by ESI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
13:12
RW
0
PAM1_HIENABLE. 0C4000-0C7FFF Attribute (HIENABLE) This field controls
the steering of read and write cycles that address the BIOS area from 0C4000
to 0C7FFF.
00: DRAM Disabled: All accesses are directed to ESI.
01: Read Only: All reads are sent to DRAM. All writes are forwarded to ESI.
10: Write Only: All writes are send to DRAM. Reads are serviced by ESI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
00: DRAM Disabled: All accesses are directed to ESI.
01: Read Only: All reads are sent to DRAM. All writes are forwarded to ESI.
10: Write Only: All writes are send to DRAM. Reads are serviced by ESI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
9:8
RW
0
PAM1_LOENABLE. 0C0000-0C3FFF Attribute (LOENABLE) This field controls
the steering of read and write cycles that address the BIOS area from 0C0000
to 0C3FFF.
00: DRAM Disabled: All accesses are directed to ESI.
01: Read Only: All reads are sent to DRAM. All writes are forwarded to ESI.
10: Write Only: All writes are send to DRAM. Reads are serviced by ESI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
00: DRAM Disabled: All accesses are directed to ESI.
01: Read Only: All reads are sent to DRAM. All writes are forwarded to ESI.
10: Write Only: All writes are send to DRAM. Reads are serviced by ESI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
5:4
RW
0
PAM0_HIENABLE. 0F0000-0FFFFF Attribute (HIENABLE) This field controls
the steering of read and write cycles that address the BIOS area from 0F0000
to 0FFFFF.
00: DRAM Disabled: All accesses are directed to ESI.
01: Read Only: All reads are sent to DRAM. All writes are forwarded to ESI.
10: Write Only: All writes are send to DRAM. Reads are serviced by ESI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
00: DRAM Disabled: All accesses are directed to ESI.
01: Read Only: All reads are sent to DRAM. All writes are forwarded to ESI.
10: Write Only: All writes are send to DRAM. Reads are serviced by ESI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
Device:
0
Function: 1
Offset:
40h
Access as a Dword
Bit
Type
Reset
Value
Description