IBM Intel Xeon E5504 46M1078 User Manual

72

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

This register provides the current and available operating conditions for the Intel QPI 
PLLs.

This register holds the next PLL multiplier. The write to one link will affect the mirror 
port as well as both Intel QPI links. The reads are link specific.

30:24

RO

-

MAX_CCLK_RATIO. Maximum CCLK (The Intel® QuickPath Interconnect 

Forwarded Clock for at speed operation) supported on this part (Value * 

133Mhz).

22:16

RO

-

MIN_CCLK_RATIO. Minimum CCLK (The Intel® QuickPath Interconnect 

Forwarded Clock for at speed operation) supported on this part (Value * 

133Mhz).

14:8

RO

-

CCLK_RATIO_MASK. Mask that will be applied to the 

QPI_[0,1]_PLL_RATIO.NEXT_PLL_RATIO field on reset to obtain the current 

ratio (I.E. mask of 1 will force only even ratios; mask of 3 forces every 4th 

ratio).

6:0

RO

-

CURRENT_CCLK_RATIO. The current CCLK (The Intel® QuickPath 

Interconnect Forwarded Clock for at speed operation) (Value * 133Mhz).

6:0

RW

12

NEXT_PLL_RATIO. The next Intel QPI PLL ratio to be adopted.