IBM Intel Xeon E5504 46M1078 User Manual

74

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

MC Primary Status register.

SMI DIMM error threshold overflow status register. This bit is set when the per-DIMM 
error counter exceeds the specified threshold. The bit is reset by BIOS.

4

RO

1

ECC_ENABLED. ECC is enabled.

2

RO

0

CHANNEL2_DISABLED. Channel 2 is disabled. This can be factory configured 

or if Init done is written without the channel_active being set. Clocks in the 

channel will be disabled when this bit is set.

1

RO

0

CHANNEL1_DISABLED. Channel 1 is disabled. This can be factory configured 

or if Init done is written without the channel_active being set. Clocks in the 

channel will be disabled when this bit is set.

0

RO

0

CHANNEL0_DISABLED. Channel 0 is disabled. This can be factory configured 

or if Init done is written without the channel_active being set. Clocks in the 

channel will be disabled when this bit is set.

13:12

RW0C

0

REDUNDANCY_LOSS_FAILING_DIMM. The ID for the failing DIMM when 

redundancy is lost.