IBM Intel Xeon E5504 46M1078 User Manual

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Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

TAD DRAM rules. Address map for channel determination within a package. All 
addresses sent to this HOME agent must hit a valid enabled DRAM_RULE. No error will 
be generated if they do not and memory aliasing will happen.

19:6

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LIMIT. DRAM rule top limit address. Must be strictly greater than previous 

rule, even if this rule is disabled, unless this rule and all following rules are 

disabled. Lower limit is the previous rule (or 0 if it is the first rule).

2:1

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MODE. DRAM rule interleave mode. If a DRAM_RULE hits, a 3-bit number is 

used to index into the corresponding interleave_list to determine which 

channel the DRAM belongs to. This mode selects how that number is 

computed. 
00: Address bits {8,7,6}. 
01: Address bits {8,7,6} XORed with {18,17,16}. 
10: Address bit {6}, MOD3(Address[39..6]). (Note 6 is the high order bit) 
11: reserved. 

0

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ENABLE. Enable for DRAM rule.