IBM Intel Xeon E5504 46M1078 User Manual
Product codes
46M1078
Register Description
82
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
2.13
Integrated Memory Controller RAS Registers
2.13.1
MC_SSRCONTROL
Scrubbing control. This register allows the enabling of patrol scrubbing and demand
scrubbing.
scrubbing.
9:8
RW
-
Logical Channel2. Index 010 of the Interleave List. Bits determined from
the matching TAD_DRAM_RULE mode.
00 – Logical channel 0
01 – Logical channel 1
10 – Logical channel 2
11 – Reserved
01 – Logical channel 1
10 – Logical channel 2
11 – Reserved
5:4
RW
-
Logical Channel1. Index 001 of the Interleave List. Bits determined from
the matching TAD_DRAM_RULE mode.
00 – Logical channel 0
01 – Logical channel 1
10 – Logical channel 2
11 – Reserved
01 – Logical channel 1
10 – Logical channel 2
11 – Reserved
1:0
RW
-
Logical Channel0. Index 000 of the Interleave List. Bits determined from
the matching TAD_DRAM_RULE mode.
00 – Logical channel 0
01 – Logical channel 1
10 – Logical channel 2
11 – Reserved
01 – Logical channel 1
10 – Logical channel 2
11 – Reserved
Device:
3
Function: 1
Offset:
C0h, C4h, C8h, CCh, D0h, D4h, D8h, DCh
Access as a Dword
Bit
Type
Reset
Value
Description
Device:
3
Function: 2
Offset:
48h
Access as a Dword
Bit
Type
Reset
Value
Description
14:7
RW
0
SCRATCHPAD. This field is available as a scratchpad for Scrubbing operations.
6
RW
0
DEMAND_SCRUB_EN. Enable Demand Scrubs.
1:0
RW
0
SSR_MODE. Patrol scrub enable.
00: Disable Patrol Scrub
01: Enable Patrol Scrub
10: RSVD.
00: Disable Patrol Scrub
01: Enable Patrol Scrub
10: RSVD.