IBM Intel Xeon E5504 46M1078 User Manual

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

83

Contains the Scrub control parameters and status.

RAS enables register.

RAS status register.

26

RW

0

SCRUBISSUED. When Set, the scrub address registers contain the last scrub 

address issued.

25

RW

0

ISSUEONCE. When Set, the patrol scrub engine will issue the address in the 

scrub address registers only once and stop.

24

RW

0

STARTSCRUB. When Set, the Patrol scrub engine will start from the address in 

the scrub address registers. Once the scrub is issued this bit is reset.

23:0

RW

0

SCRUBINTERVAL. Defines the interval in DCLKS between patrol scrub 

requests. The calculation for this register to get a scrub to every line in 24 

hours is:
((36400)/(memory capacity/64))/cycle time of DCLK.

For 512MB at DDR3-800:
(36400/((2^29)/64))/1.25 x 10^-9 = 3471374 = 0x34F80E.

1

RW

0

LOCKSTEPEN. Lockstep enable. When set, channel 0 and 1 are tied together 

in lockstep. The channel mapper register must be appropriately programmed 

as well.

0

RW

0

MIRROREN. Mirror mode enable. The channel mapping must be set up 

before this bit will have an effect on Integrated Memory Controller operation. 

This changes the error policy and alternates reads between channels.

0

RW

0

REDUNDANCY_LOSS. One channel of a mirrored pair had an uncorrectable 

error and redundancy has been lost. This bit is set by hardware and must be 

cleared by software performing a channel reset to regain mirrored status.