IBM Intel Xeon E5504 46M1078 User Manual

Product codes
46M1078
Page of 130
Register Description
86
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
2.14.3
MC_TEST_PH_CTR
Memory test Control Register
2.14.4
MC_TEST_PH_PIS
Memory test physical layer initialization status
2.14.5
MC_TEST_PAT_GCTR
Pattern Generator Control
Device:
3
Function: 4
Offset:
6Ch
Access as a Dword
Bit
Type
Reset
Value
Description
10:8
RW
0
INIT_MODE: Initialization Mode
Idle: 000
Loopback: 001
Memtest: 110
Meminit: 111
Device:
3
Function: 4
Offset:
80h
Access as a Dword
Bit
Type
Reset
Value
Description
29
RO
-
GLOBAL_ERROR: Indication that an error was detected during a memory test.
Device:
3
Function: 4
Offset:
A8h
Access as a Dword
Bit
Type
Reset
Value
Description
28:24
RW
6
EXP_LOOP_CNT: Sets the length of the test, defined as 2^(EXP_LOOP_CNT)
21
RW
0
ERROR_COUNT_STALL: Masks all detected errors until cleared
20
RW1S
0
STOP_TEST: Force exit from Loopback.Pattern
19
RW
0
DRIVE_DC_ZERO: Drive 0 on lanes with PAT_DCD asserted
13:12
RW
0
PATBUF_WD_SEL: Select word within pattern buffer to be written
10:9
RW
0
PATBUF_SEL: Select which pattern buffer will be written when 
MC_TEST_PAT_BA is written
5
RW
0
IGN_REM_PARAM: Slave will ignore remote parameters transmitted in 
Loopback.Marker
4
RW
0
ENABLE_LFSR2: Use scrambled output of Pattern Buffer 2
3
RW
0
ENABLE_LFSR1: Use scrambled output of Pattern Buffer 1
2
RW
1
ENABLE_AUTOINV: Inversion pattern register will rotate automatically once 
per loop
1
RW
0
STOP_ON_ERROR: Exit Loopback.Pattern upon first detected error
0
RW1S
0
START_TEST: Initiate transition to Loopback.Pattern