IBM Intel Xeon E5504 46M1078 User Manual

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

89

Initialization sequence parameters are stored in this register. Each field is 2^n count. 

Bits [24:22] control the logical to physical rank mapping. The Integrated Memory 
Controller needs to know the location of different ranks in order to drive the proper chip 
selects (CS#) and Clock Enable (CKE). Each valid combination results in a different 
mapping of CS or CKE connections to the logical ranks. The table below summarizes 
the supported combinations.

7:5

RW

0

RANK. The rank currently being tested. The PhyInit FSM must be sequenced 

for every rank present in the channel. The rank value is set to the rank being 

trained.

4:2

RW

0

NXT_PHYINIT_STATE. Set to sequence the physical layer state machine.
000: IDLE
001: RD DQ-DQS
010: RcvEn Bitlock
011: Write Level 
100: WR DQ-DQS.

1

RW

0

AUTODIS. Disables the automatic training where each step is automatically 

incremented. When set, the physical layer state machine must be sequenced 

with software. The training FSM must be sequenced using the 

NXT_PHYINIT_STATE field.

0

WO

0

TRAIN. Cycle through the training sequence for the rank specified in the RANK 

field. 

1

0

0

3 DIMMs Per Channel (6ODT/6CS)

0

1

1

Single Quad Rank (2ODT/4CS)

0

0

1

Quad Rank plus another DIMM (4ODT/8CS)

0

0

0

All other configurations.