IBM Intel Xeon E5504 46M1078 User Manual

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

99

This register contains parameters that specify the bank timing parameters. These 
values are in DCLK. The values in these registers are encoded where noted. All of these 
values apply to commands to the same rank only.

This register contains parameters that specify the refresh timings. Units are in DCLK.

21:17

RW

0

tWTPr. Minimum Write CAS to Precharge command delay.

16:13

RW

0

tRTPr. Minimum Read CAS to Precharge command delay.

12:9

RW

0

tRCD. Minimum delay between Activate and CAS commands.

8:4

RW

0

tRAS. Minimum delay between Activate and Precharge commands.

3:0

RW

0

tRP. Minimum delay between Precharge command and Activate command.

29:19

RW

0

tTHROT_OPPREF. The minimum time between two opportunistic refreshes. 

Should be set to tRFC in DCLKS. Zero is an invalid encoding. A value of 1 should 

be programmed to disable the throttling of opportunistic refreshes. By setting this 

field to tRFC, current to a single DIMM can be limited to that required to support 

this scenario without significant performance impact: 
- 8 panic refreshes in tREFI to one rank 
- 1 opportunistic refresh every tRFC to another rank 
- full bandwidth delivered by the third and fourth ranks 
Platforms that can supply peak currents to the DIMMs should disable opportunistic 

refresh throttling for max performance.

18:9

RW

0

tREFI_8. Average periodic refresh interval divided by 8.

8:0

RW

0

tRFC. Delay between the refresh command and an activate or refresh command.