IBM Intel Xeon E5506 46M1079 User Manual
Product codes
46M1079
Introduction
10
Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 1
• 1-Socket Workstation Platforms support Intel Xeon Processor 5500 Series SKUs.
These platforms enable a wide range of options for either the performance, power,
or cost sensitive customer.
or cost sensitive customer.
Note:
All references to “chipset” in this document pertain to the Intel
®
5520 chipset and
Intel
®
5500 chipset, unless specifically stated otherwise.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested.
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested.
A ‘_N’ and ‘_P’ after a signal name refers to a differential pair.
Commonly used terms are explained here for clarification:
• 1366-land FC-LGA package — The Intel Xeon Processor 5500 Series is available
in a Flip-Chip Land Grid Array (FC-LGA) package, consisting of processor mounted
on a land grid array substrate with an integrated heat spreader (IHS).
on a land grid array substrate with an integrated heat spreader (IHS).
• DDR3 — Double Data Rate 3 synchronous dynamic random access memory
(SDRAM) is the name of the new DDR memory standard that is being developed as
the successor to DDR2 SDRAM.
the successor to DDR2 SDRAM.
• Enhanced Intel SpeedStep Technology — Enhanced Intel SpeedStep
Technology allows the operating system to reduce power consumption when
performance is not needed.
performance is not needed.
• Intel Turbo Boost Technology — Intel Turbo Boost Technology is a way to
automatically run the processor core faster than the marked frequency if the part is
operating under power, temperature, and current specifications limits of the
Thermal Design Power (TDP). This results in increased performance of both single
and multi-threaded applications.
operating under power, temperature, and current specifications limits of the
Thermal Design Power (TDP). This results in increased performance of both single
and multi-threaded applications.
• Execute Disable Bit — Execute Disable allows memory to be marked as
executable or non-executable, when combined with a supporting operating system.
If code attempts to run in non-executable memory the processor raises an error to
the operating system. This feature can prevent some classes of viruses or worms
that exploit buffer over run vulnerabilities and can thus help improve the overall
security of the system. See the Intel
If code attempts to run in non-executable memory the processor raises an error to
the operating system. This feature can prevent some classes of viruses or worms
that exploit buffer over run vulnerabilities and can thus help improve the overall
security of the system. See the Intel
®
64 and IA-32 Architecture Software
Developer's Manuals for more detailed information.
• Functional Operation — Refers to the normal operating conditions in which all
processor specifications, including DC, AC, signal quality, mechanical, and thermal,
are satisfied.
are satisfied.
Table 1-1.
Intel Xeon Processor 5500 Series Feature Set Overview
Feature
Intel Xeon Processor 5500 Series
Cache Sizes
- Instruction Cache = 32 KB, per core
- Data Cache = 32 KB, per core
- 256 KB Mid-Level Cache per core
- 8 MB shared among cores (up to 4)
- 256 KB Mid-Level Cache per core
- 8 MB shared among cores (up to 4)
Data Transfer Rate
Two (2) full-width Intel QuickPath Interconnect links, up to 6.4 GT/s in
each direction
Multi-Core Support
Up to 4 Cores per processor
Dual Processor Support
Up to 2 processors per platform
Package
1366-land FCLGA