IBM Intel Xeon E5506 46M1079 User Manual
Product codes
46M1079
Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 1
135
Features
than C1/C1E but the package low power state is limited to C1/C1E via the
PMG_CST_CONFIG_CONTROL MSR. In the C1E state, the processor will automatically
transition to the lowest power operating point (lowest supported voltage and associated
frequency). When entering the C1E state, the processor will first switch to the lowest
bus ratio and then transition to the lower VID. No notification to the system occurs
upon entry to C1/C1E.
PMG_CST_CONFIG_CONTROL MSR. In the C1E state, the processor will automatically
transition to the lowest power operating point (lowest supported voltage and associated
frequency). When entering the C1E state, the processor will first switch to the lowest
bus ratio and then transition to the lower VID. No notification to the system occurs
upon entry to C1/C1E.
To operate within specification, BIOS must enable the C1E feature for all installed
processors.
processors.
7.2.2.3
Package C3 State
The package will enter the C3 low power state when all cores are in the C3 or lower
power state and the processor has been granted permission by the other component(s)
in the system to enter the C3 state. The package will also enter the C3 state when all
cores are in an idle state lower than C3 but other component(s) in the system have
only granted permission to enter C3.
power state and the processor has been granted permission by the other component(s)
in the system to enter the C3 state. The package will also enter the C3 state when all
cores are in an idle state lower than C3 but other component(s) in the system have
only granted permission to enter C3.
If Intel QuickPath Interconnect L1 has been granted, the processor will disable some
clocks and PLLs and for processors with an Integrated Memory Controller, the DRAM
will be put into self-refresh.
clocks and PLLs and for processors with an Integrated Memory Controller, the DRAM
will be put into self-refresh.
7.2.2.4
Package C6 State
The package will enter the C6 low power state when all cores are in the C6 or lower
power state and the processor has been granted permission by the other component(s)
in the system to enter the C6 state. The package will also enter the C6 state when all
cores are in an idle state lower than C6 but the other component(s) have only granted
permission to enter C6.
power state and the processor has been granted permission by the other component(s)
in the system to enter the C6 state. The package will also enter the C6 state when all
cores are in an idle state lower than C6 but the other component(s) have only granted
permission to enter C6.
If Intel QuickPath Interconnect L1 has been granted, the processor will disable some
clocks and PLLs and the shared cache will enter a deep sleep state. Additionally, for
processors with an Integrated Memory Controller, the DRAM will be put into self-
refresh.
clocks and PLLs and the shared cache will enter a deep sleep state. Additionally, for
processors with an Integrated Memory Controller, the DRAM will be put into self-
refresh.
7.2.3
Intel® Xeon® Processor 5500 Series C-State Power
Specifications
lists C-State power specifications for various Intel Xeon processor 5500 series
SKUs.
Table 7-3.
Processor C-State Power Specifications
Package
C-State
C-State
1
Notes:
1. Specifications are at T
case
= 50C with all cores in the specified C-State.
130W
95W
80W
2
2. Standard/Basic SKUs.
60W
3
3. Applies to Low Power SKU and Intel
®
Xeon
®
Processor L5518.
38W
C1E
35 W
30 W
30/40 W
22 W
16 W
C3
30 W
26 W
26/35 W
18 W
12 W
C6
12 W
10 W
10/15 W
8 W
8 W