IBM Intel Xeon E5506 46M1079 User Manual
Product codes
46M1079
Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 1
23
Intel® Xeon® Processors 5500 Series Electrical Specifications
2.1.8
Reserved or Unused Signals
All Reserved (RSVD) signals must remain unconnected. Connection of these signals to
V
V
CC
, V
TTA
, V
TTD
, V
DDQ
, V
SS
, or any other signal (including each other) can result in
for the
land listing and the location of all Reserved signals.
For reliable operation, connect unused inputs or bidirectional signals to an appropriate
signal level. Unused Intel QuickPath Interconnect input and output pins can be left
floating. Unused active high inputs should be connected through a resistor to ground
(V
signal level. Unused Intel QuickPath Interconnect input and output pins can be left
floating. Unused active high inputs should be connected through a resistor to ground
(V
SS
). Unused outputs can be left unconnected; however, this may interfere with some
TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor
must be used when tying bidirectional signals to power or ground. When tying any
signal to power or ground, including a resistor will also allow for system testability.
Resistor values should be within ± 20% of the impedance of the baseboard trace,
unless otherwise noted in the appropriate platform design guidelines.
must be used when tying bidirectional signals to power or ground. When tying any
signal to power or ground, including a resistor will also allow for system testability.
Resistor values should be within ± 20% of the impedance of the baseboard trace,
unless otherwise noted in the appropriate platform design guidelines.
TAP signals do not include on-die termination, however they may include resistors on
package (refer to
package (refer to
for details). Inputs and utilized outputs must be
terminated on the baseboard. Unused outputs may be terminated on the baseboard or
left unconnected. Note that leaving unused outputs unterminated may interfere with
some TAP functions, complicate debug probing, and prevent boundary scan testing.
left unconnected. Note that leaving unused outputs unterminated may interfere with
some TAP functions, complicate debug probing, and prevent boundary scan testing.
2.2
Signal Group Summary
Signals are combined in
by buffer type and characteristics. “Buffer Type”
denotes the applicable signaling technology and specifications.
Table 2-4.
V
TT
Voltage Identification Definition
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VR 11.0
Voltage
V
TT_TYP
(Voltage + Offset)
0
1
0
0
0
0
1
0
1.200V
1.220V
0
1
0
0
0
1
1
0
1.175V
1.195V
0
1
0
0
1
0
1
0
1.150V
1.170V
0
1
0
0
1
1
1
0
1.125V
1.145V
0
1
0
1
0
0
1
0
1.100V
1.120V
0
1
0
1
0
1
1
0
1.075V
1.095V
0
1
0
1
1
0
1
0
1.050V
1.070V
0
1
0
1
1
1
1
0
1.025V
1.045V
Table 2-5.
Signal Groups (Sheet 1 of 2)
Signal Group
Buffer Type
Signals
1
Intel
QuickPath Interconnect Signals
Differential
Intel
QuickPath Interconnect Input
QPI[0/1]_DRX_D[N/P][19:0],
QPI[0/1]_CLKRX_DP, QPI[0/1]_CLKRX_DN
Differential
Intel
QuickPath Interconnect Output
QPI[0/1]_DTX_D[N/P][19:0],
QPI[0/1]_CLKTX_DP, QPI[0/1]_CLKTX_DN
Single ended
Analog Input
QPI[0/1]_COMP
DDR3 Reference Clocks
2
Differential
Output
DDR{0/1/2}_CLK_[P/N][3:0]