IBM Intel Xeon E5506 46M1079 User Manual
Product codes
46M1079
Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 1
25
Intel® Xeon® Processors 5500 Series Electrical Specifications
Signals that include on-die termination (ODT) are listed in
.
Notes:
1.
Unless otherwise specified, signals have ODT in the package with a 50 Ω pull-down to V
SS
.
2.
Unless otherwise specified, all DDR3 signals are terminated to V
DDQ
/2.
3.
DDR{0/1/2}_PAR_ERR#[2:0] are terminated to V
DDQ.
4.
TCK does not include ODT, this signal is weakly pulled-down via a 1-5 kΩ resistor to V
SS
.
5.
TDI, TMS, TRST# do not include ODT, these signals are weakly pulled-up via 1-5kΩ resistor to V
TT
.
6.
BPM[7:0]# and PREQ# signals have ODT in package with 35 Ω pull-ups to V
TT.
7.
PECI_ID# has ODT in package with a 1-5 kΩ pull-up to V
TT
.
8.
VCCPWRGOOD, VDDPWRGOOD, and VTTPWRGOOD have ODT in package with a 5-20 kΩ pull-down to V
SS
.
2.3
Mixing Processors
Intel supports dual processor (DP) configurations consisting of processors:
1. from the same power optimization segment
2. that support the same maximum Intel QuickPath Interconnect and DDR3 memory
2. that support the same maximum Intel QuickPath Interconnect and DDR3 memory
speeds
3. that share symmetry across physical packages with respect to the number of
logical processor per package, number of cores per package, number of Intel
QuickPath interfaces, and cache topology
QuickPath interfaces, and cache topology
4. that have identical Extended Family, Extended Model, Processor Type, Family Code
and Model Number as indicated by the function 1 of the CPUID instruction
Note:
Processors must operate with the same Intel QuickPath Interconnect, DDR3 memory,
and core frequency.
While Intel does nothing to prevent processors from operating together, some
combinations may not be supported due to limited validation, which may result in
uncharacterized errata. Coupling this fact with the large number of Intel Xeon
Processor 5500 series attributes, the following population rules and stepping matrix
have been developed to clearly define supported configurations.
combinations may not be supported due to limited validation, which may result in
uncharacterized errata. Coupling this fact with the large number of Intel Xeon
Processor 5500 series attributes, the following population rules and stepping matrix
have been developed to clearly define supported configurations.
1. Processors must be of the same power-optimization segment. This insures
processors include the same maximum Intel QuickPath interconnect and DDR3
operating speeds and cache sizes.
Notes:
1. Refer to
for land assignments and
for signal definitions.
2. DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel1 and DDR3 Channel 2.
Table 2-6. Signals With On-Die Termination (ODT)
Intel QuickPath Interface Signal Group
1
QPI[1:0]_DRX_DP[19:0], QPI[1:0]_DRX_DN[19:0], QPI[1:0]_TRX_DP[19:0], QPI[1:0]_TRX_DN[19:0],
QPI[0/1]_CLKRX_D[N/P], QPI[0/1]_CLKTX_D[N/P]
DDR3 Signal Group
2
DDR{0/1/2}_DQ[63:0], DDR{0/1/2}_DQS_[N/P][17:0], DDR{0/1/2}_ECC[7:0],
DDR{0/1/2}_PAR_ERR#[2:0]
3
Processor Sideband Signal Group
BPM#[7:0]
6
, PECI_ID#
7
, PREQ#
6
Test Access Port (TAP) Signal Group
TCK
4
, TDI
5
, TMS
5
, TRST#
5
Power/Other Signal Group
8
VCCPWRGOOD, VDDPWRGOOD, VTTPWRGOOD