Intel C2D Mobile T5800 LF80537GG041F User Manual
Product codes
LF80537GG041F
Introduction
8
Datasheet
• Digital thermal sensor (DTS)
• Intel® 64 architecture
• Supports enhanced Intel® Virtualization Technology
• Enhanced Intel® Dynamic Acceleration Technology and Enhanced Multi-Threaded
• Intel® 64 architecture
• Supports enhanced Intel® Virtualization Technology
• Enhanced Intel® Dynamic Acceleration Technology and Enhanced Multi-Threaded
Thermal Management (EMTTM)
• Supports PSI2 functionality
• SV processor offered in Micro-FCPGA and Micro-FCBGA packaging technologies
• Processor in POP, LV and ULV are offered in Micro-FCBGA packaging technologies
• SV processor offered in Micro-FCPGA and Micro-FCBGA packaging technologies
• Processor in POP, LV and ULV are offered in Micro-FCBGA packaging technologies
only
• Execute Disable Bit support for enhanced security
• Intel® Deep Power Down low-power state with P_LVL6 I/O support
• Support for Intel® Trusted Execution Technology
• Half ratio support (N/2) for core to bus ratio
• Intel® Deep Power Down low-power state with P_LVL6 I/O support
• Support for Intel® Trusted Execution Technology
• Half ratio support (N/2) for core to bus ratio
1.1
Terminology
Term
Definition
#
A “#” symbol after a signal name refers to an active low signal, indicating a
signal is in the active state when driven to a low level. For example, when
RESET# is low, a reset has been requested. Conversely, when NMI is high,
a nonmaskable interrupt has occurred. In the case of signals where the
name does not imply an active state but describes part of a binary
sequence (such as address or data), the “#” symbol implies that the signal
is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]#
= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
signal is in the active state when driven to a low level. For example, when
RESET# is low, a reset has been requested. Conversely, when NMI is high,
a nonmaskable interrupt has occurred. In the case of signals where the
name does not imply an active state but describes part of a binary
sequence (such as address or data), the “#” symbol implies that the signal
is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]#
= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
Front Side Bus
(FSB)
(FSB)
Refers to the interface between the processor and system core logic (also
known as the chipset components).
known as the chipset components).
AGTL+
Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+
signaling technology on some Intel processors.
signaling technology on some Intel processors.
Storage
Conditions
Conditions
Refers to a non-operational state. The processor may be installed in a
platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor landings should not
be connected to any supply voltages, have any I/Os biased or receive any
clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device
removed from packaging material) the processor must be handled in
accordance with moisture sensitivity labeling (MSL) as indicated on the
packaging material.
platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor landings should not
be connected to any supply voltages, have any I/Os biased or receive any
clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device
removed from packaging material) the processor must be handled in
accordance with moisture sensitivity labeling (MSL) as indicated on the
packaging material.
Enhanced Intel
SpeedStep®
Technology
SpeedStep®
Technology
Technology that provides power management capabilities to laptops.
Processor Core
Processor core die with integrated L1 and L2 cache. All AC timing and signal
integrity specifications are at the pads of the processor core.
integrity specifications are at the pads of the processor core.