Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual

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Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

The Intel TXT registers adhere to the public and private attributes described in XREF.

As described previously, each Intel TXT register may have up to three ways to access it. 
These are given the following symbolic names. TXT_TXT is the memory region starting 
at FED2_0000h when it is accessed using the special Intel TXT read or write 
commands. TXT_PR is the memory region starting at FED2_0000h when it is accessed 
using normal read or write commands. TXT_PB is the memory region starting at 
FED3_0000h accessed using any read or write command. TXT_PB_noWR is similar to 
TXT_PB but write accesses have no affect. 

The register tables below sometimes list more than one base for a register. Normally 
this would indicate that there is more than one register. However, in the current section 
it indicates that there is a single register which can be accessed in more than one way.

This register is used to read the status of the Intel TXT Command/Status Engine 
functional block in the Shortened Product Name.

General Behavioral Rules:

• This is a read-only register, so writes to this register will be ignored.
• This register is available in both the Public and Private Intel TXT configuration 

spaces.

31:18

RV

0h

Reserved

17

RO

0

TXT.SEQ.IN.PROGRESS 
This bit is set when the TXT.SEQUENCE.START msg is received from a 

processor.
This bit is cleared when the TXT.SEQUENCE.DONE msg is received from a 

processor.
If this bit is set and the chipset receives another TXT.SEQUENCE.START 

message, then the chipset treats this as a rogue attack and does TXT_RESET# 

and sets Rogue status bit. 

16

RO

0

TXT.LOCALITY2.OPEN.STS 
This bit is set when either the TXT.CMD.OPEN.LOCALITY2 command or the 

TXT.CMD.OPEN.PRIVATE is seen by the chipset. It is cleared on reset or when 

either TXT.CMD.CLOSE.LOCALITY2 or TXT.CMD.CLOSE.PRIVATE is seen. This 

bit can be used by sw as a positive indication that the command has taken 

effect. Note that hardware should not set or clear this bit until the internal 

hardware will guarantee that incoming cycles will be decoded based on the 

state change caused by the OPEN or CLOSE command.

15

RO

0

TXT.LOCALITY1.OPEN.STS
This bit is set when the TXT.CMD.OPEN.LOCALITY1 command is seen by the 

chipset. It is cleared on reset or when TXT.CMD.CLOSE.LOCALITY1 is seen. 

This bit can be used by sw as a positive indication that the command has 

taken effect. Note that hardware should not set or clear this bit until the 

internal hardware will guarantee that incoming cycles will be decoded based 

on the state change caused by the OPEN or CLOSE command.