Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

205

Register for legacy device 0, function 0, 90h–93h address space.

5

RO

0

66-MHz Capable
Does not apply to PCI Express. Must be hardwired to 0.

4

RO

1

Capability List (CLIST)
This bit is hardwired to 1 to indicate to the configuration software that this 

device/function implements a list of new capabilities. A list of new capabilities 

is accessed using registers CAPPTR at the configuration address offset 34h 

from the start of the PCI configuration space header of this function. Register 

CAPPTR contains the offset pointing to the start address with configuration 

space of this device where the capability register resides. This bit must be set 

for a PCI Express device or the VSEC capability.
If no capability structures are implemented, this bit is hardwired to 0.

3

RO

0

Interrupt Status 
If this device generates an interrupt, then this read-only bit reflects the state 

of the interrupt in the device/function. Only when the Interrupt Disable bit in 

the command register is a 0 and this Interrupt Status bit is a 1, will the 

device’s/function’s INTx# signal be asserted. Setting the Interrupt Disable bit 

to a 1 has no effect on the state of this bit.
If this device does not generate interrupts, then this bit is not implemented 

(RO and reads returns 0).

2:0

RO

0

31:29

RO

0

29:28

RW

0

PAM3_HIENABLE. 0D4000–0D7FFFh Attribute (HIENABLE) This field controls 

the steering of read and write cycles that address the BIOS area from 

0D4000h to 0D7FFFh. 
00 = DRAM Disabled — All accesses are directed to DMI.
01 = Read Only — All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only — All writes are send to DRAM. Reads are serviced by DMI. 
11 = Normal DRAM Operation — All reads and writes are serviced by DRAM.