Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Processor Uncore Configuration Registers
214
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
4.7
Integrated Memory Controller Control Registers
4.7.1
MC_CONTROL
Primary control register.
5:4
RWST
0
LLR_TO_LINK_RESET
Consecutive LLRs to Link Reset — Sticky, Late action.
00 = up to 16
01 = up to 8
10 = up to 4
11 = 0, disable LLR (if CRC error, immediate error condition).
Consecutive LLRs to Link Reset — Sticky, Late action.
00 = up to 16
01 = up to 8
10 = up to 4
11 = 0, disable LLR (if CRC error, immediate error condition).
3:2
RWST
0
LINK_RESET_FROM_LLR
Consecutive Link Reset from LLR till error condition (only applies if LLR enabled)
Consecutive Link Reset from LLR till error condition (only applies if LLR enabled)
— Sticky, Late action.
00 = up to 2
01 = up to 1
10 = up to 0
11 = Reserved.
00 = up to 2
01 = up to 1
10 = up to 0
11 = Reserved.
1
RW
0
LINK_HARD_RESET. Link Hard Reset
Re-initialize resetting values in sticky registers. Write 1 to reset this link. This is
Re-initialize resetting values in sticky registers. Write 1 to reset this link. This is
a destructive reset. When reset asserts, register clears to 0h.
0
RW
0
LINK_SOFT_RESET. Link Soft Reset
Re-initialize without resetting sticky registers. Write 1 to reset this link. This is a
Re-initialize without resetting sticky registers. Write 1 to reset this link. This is a
destructive reset. When reset asserts, register clears to 0h.
Device:
2
Function: 0
Offset:
48h
Access as a DWord
Bit
Type
Default
Description
Device:
3
Function: 0
Offset:
48h
Access as a DWord
Bit
Attr
Default
Description
31:8
RO
0
Reserved
9
RW
0
CHANNEL1_ACTIVE
When set, indicates MC channel 1 is active. This bit is controlled (set/reset)
When set, indicates MC channel 1 is active. This bit is controlled (set/reset)
by software only. This bit is required to be set for any active channel when
INIT_DONE is set by software.
8
RW
0
CHANNEL0_ACTIVE
When set, indicate MC channel 0 is active. This bit is controlled (set/reset)
When set, indicate MC channel 0 is active. This bit is controlled (set/reset)
by software only. This bit is required to be set for any active channel when
INIT_DONE is set by software.
7
WO
0
INIT_DONE
MC initialize complete signal. Setting this bit will exit the training mode of
MC initialize complete signal. Setting this bit will exit the training mode of
the Integrated Memory Controller and begin normal operation including all
enabled maintenance operations. Any CHANNNEL_ACTIVE bits not set
when writing a 1 to INIT_DONE will cause the corresponding channel to be
disabled.