Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual

Product codes
BX80605X3430
Page of 296
Processor Uncore Configuration Registers
220
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
4.7.9
MC_RD_CRDT_INIT
These registers contain the initial read credits available for issuing memory reads. TAD 
read credit counters are loaded with the corresponding values at reset and anytime this 
register is written. BIOS must initialize this register with appropriate values depending 
on the level of Isoch support in the platform. It is illegal to write this register while TAD 
is active (has memory requests outstanding), as the write will break TAD's outstanding 
credit count values. 
Register programming rules:
• Total read credits (CRDT_RD + CRDT_RD_HIGH + CRDT_RD_CRIT) must not 
exceed 31.
• CRDT_RD_HIGH value must correspond to the number of high RTIDs reserved at 
the IIH.
• CRDT_RD_CRIT value must correspond to the number of critical RTIDs reserved at 
the IIH.
• CRDT_RD_HIGH + CRDT_RD must be less than or equal to 13.
• CRDT_RD_HIGH + CRDT_RD_CRIT must be less than or equal to 8.
• CRDT_RD_CRIT must be less than or equal to 6. Set CRDT_RD to (16 - 
CRDT_RD_CRIT - CRDT_RD_HIGH).
• Max for CRDT_RD is 15. 
• If (Isoch not enabled) then CRDT_RD_HIGH and CRDT_RD_CRIT are set to 0.
Device:
3
Function: 0
Offset:
70h
Access as a DWord
Bit
Attr
Default
Description
31:21
RO
0
Reserved
20:16
RW
3
CRDT_RD_CRIT
Critical Read Credits.
15:13
RO
0
Reserved
12:8
RW
1
CRDT_RD_HIGH
High Read Credits.
7:5
RO
0
Reserved
4:0
RW
13
CRDT_RD
Normal Read Credits.