Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual
Product codes
BX80605X3430
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
227
Processor Uncore Configuration Registers
A write operation is performed by writing the payload in the data register including
mask and halt bits. The appropriate scan chain is selected in the scan chain select
register. The index (offset +length of section –1) is written into the control register
along with the write bit. The write is complete when the write bit is cleared. The write is
complete when the write bit in the control register is cleared by the Integrated Memory
Controller. For optimization adjacent sections that fit within 32 bits may be written
together. For example a write to adjacent sections 40 (length 11 bits), 51 (length
11 bits) and 62 (length 8 bits) can be written in one write operation because they are a
total of 30 bits which fits in the data register without overlap into other sections.
Section 40 would be shifted eft by 30 bits into the data register. Section 51 would be
shifted left 20 bits into the data register. Section 62 would be shifted left by 8 bits into
the data register. Bit positions 31 and 30 would be left over as zeros in the data
register. When the write operation begins Section 62 will be shifted in first followed by
sections 51 and 40. The index that is programmed into the control register in this case
would be 69 (62 + 8 – 1). Refer to
mask and halt bits. The appropriate scan chain is selected in the scan chain select
register. The index (offset +length of section –1) is written into the control register
along with the write bit. The write is complete when the write bit is cleared. The write is
complete when the write bit in the control register is cleared by the Integrated Memory
Controller. For optimization adjacent sections that fit within 32 bits may be written
together. For example a write to adjacent sections 40 (length 11 bits), 51 (length
11 bits) and 62 (length 8 bits) can be written in one write operation because they are a
total of 30 bits which fits in the data register without overlap into other sections.
Section 40 would be shifted eft by 30 bits into the data register. Section 51 would be
shifted left 20 bits into the data register. Section 62 would be shifted left by 8 bits into
the data register. Bit positions 31 and 30 would be left over as zeros in the data
register. When the write operation begins Section 62 will be shifted in first followed by
sections 51 and 40. The index that is programmed into the control register in this case
would be 69 (62 + 8 – 1). Refer to
.
4.9.3
MC_DIMM_CLK_RATIO_STATUS
Contains status information about DIMM clock ratio.
Device:
3
Function: 4
Offset:
50h
Access as a DWord
Bit
Attr
Default
Description
31:29
RO
0
Reserved
28:24
RO
0
MAX_RATIO
Maximum ratio allowed by the part.
Value – Qclk
00000 = RSVD
00010 = 266 MHz
00100 = 533 MHz
00110 = 800 MHz
01000 = 1066 MHz
01010 = 1333 MHz
Maximum ratio allowed by the part.
Value – Qclk
00000 = RSVD
00010 = 266 MHz
00100 = 533 MHz
00110 = 800 MHz
01000 = 1066 MHz
01010 = 1333 MHz
23:5
RO
0
Reserved
4:0
RO
0
QCLK_RATIO
Current ratio of Qclk.
Value – Qclk.
00000 = RSVD
00010 = 266 MHz
00100 = 533 MHz
00110 = 800 MHz
01000 = 1066 MHz
01010 = 1333 MHz
Current ratio of Qclk.
Value – Qclk.
00000 = RSVD
00010 = 266 MHz
00100 = 533 MHz
00110 = 800 MHz
01000 = 1066 MHz
01010 = 1333 MHz