Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

237

DDR3 Configuration Command. This register is used to issue commands to the DIMMs 
such as MRS commands. The register is used by setting one of the *_VALID bits along 
with the appropriate address and destination RANK. The command is then issued 
directly to the DIMM. Care must be taken in using this register as there is no 
enforcement of timing parameters related to the action taken by a DDR3CMD write.This 
register has no effect after MC_CONROL>INIT_DONE is set.

31:29

RO

0

28

RW

0

PRECHARGE_VALID
Indicates current command is for a precharge command.

27

RW

0

ACTIVATE_VALID
Indicates current command is for an activate command.

26

RW

0

REG_VALID
Indicates current command is for a registered DIMM configuration write Bit 

is cleared by hardware on issuance. This bit applies only to processors 

supporting registered DIMMs.

25

RW

0

WR_VALID
Indicates current command is for a write CAS. Bit is cleared by hardware 

on issuance.

24

RW

0

RD_VALID
Indicates current command is for a read CAS. Bit is cleared by hardware 

on issuance.

23

RW

0

MRS_VALID
Indicates current command is an MRS command. Bit is cleared by 

hardware on issuance.

22:20

RW

0

RANK
Destination rank for command.

19:16

RW

0

MRS_BA
Bank address portion of the MRS command. The MRS_BA field corresponds 

to BA[3:0].

15:0

RW

0

MRS_ADDR
Address used by the MRS command.