Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual

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Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

In addition to reserved bits within a register, the processor contains address locations 
in the configuration space of the Host Bridge entity that are marked either "Reserved" 
or “Intel Reserved”. The processor responds to accesses to “Reserved” address 
locations by completing the host cycle. When a “Reserved” register location is read, a 
zero value is returned. (“Reserved” registers can be 8, 16, or 32 bits in size). Registers 
that are marked as “Intel Reserved” must not be modified by system software. Writes 
to “Intel Reserved” registers may cause system failure. Reads from “Intel Reserved” 
registers may return a non-zero value.

Upon a Full Reset, the processor sets its entire set of internal configuration registers to 
predetermined default states. Some register values at reset are determined by external 
strapping options. The default state represents the minimum functionality feature set 
required to successfully bring up the system. Hence, it does not represent the optimal 
system configuration. It is the responsibility of the system initialization software 
(usually BIOS) to properly determine the DRAM configurations, operating parameters, 
and optional system features that are applicable, and to program the processor 
registers accordingly. 

The processor contains two registers that reside in the processor I/O address space − 

the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data 
(CONFIG_DATA) Register. The Configuration Address Register enables/disables the 
configuration space and determines what portion of configuration space is visible 
through the Configuration Data window.