Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430 User Manual

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

287

In general, software needs to guarantee that for a given address there can only be a 
single target in the system. Otherwise, it is a programming error and results are 
undefined. The one exception is that VGA addresses would fall within the inbound 
coarse decode memory range. The IIO inbound address decoder handles this conflict 
and forwards the VGA addresses to only the VGA port in the system (and not system 
memory).

This section covers address decoding that IIO performs on a transaction from Intel 
QuickPath Interconnect/JTAG that targets one of the downstream devices/ports of the 
IIO. In the description in the rest of the section, PCIe refers to all of a standard PCI 
Express port and DMI, unless noted otherwise.

• Before any transaction from Intel QuickPath Interconnect is validly decoded by IIO, 

the NodeID in the incoming transaction must match the NodeIDs assigned to the 
IIO (any exceptions are noted when required). Else it is an error. 

• All target decoding toward PCIe, firmware and internal IIO devices follow address 

based routing. Address based routing follows the standard PCI tree hierarchy 
routing

• No NodeID based routing is supported south of the Intel QuickPath Interconnect 

port in IIO

• Subtractive decode port in IIO is the port that is a) the recipient of all addresses 

that are not positively decoded towards any of the valid targets in the IIO and b) 
the recipient of all message/special cycles that are targeted at the legacy PCH. 

— In the processor, the DMI is always the subtractive port. Virtual peer-to-peer 

bridge decoding related registers with their associated control bits (for 

example, VGAEN bit) and other misc address ranges (I/OxAPIC) of a DMI port 

are NOT valid (and ignored by the IIO decoder) when it is set as the subtractive 

decoding port. Subtractive decode transactions are forwarded to the legacy 

DMI port, irrespective of the setting of the MSE/IOSE bits in that port.

• Unless specified otherwise, all addresses (no distinction made) are first positively 

decoded against all target address ranges. Valid targets are PCIe, DMI, CSR and 
Perf Mon device. Software has the responsibility to make sure that only one target 
can ultimately be the target of a given address and IIO will forward the transaction 
towards that target

.

— For outbound transactions, when no target is positively decoded, the 

transactions are sent to the downstream DMI port if it is indicated as the 

subtractive decode port. In the processor, the DMI is always the subtractive 

decode port. 

— For inbound transactions on the processor, when no target is positively 

decoded, the transactions are sent to the subtractive decode port which is DMI. 

• For positive decoding, the memory decode to each PCIe target is governed by 

Memory Space Enable (MSE) bit in the device PCI configuration space and I/O 
decode is covered by the I/O Space Enable bit in the device PCI configuration 
space. The only exceptions to this rule are the per port (external) I/OxAPIC address 
range which are decoded irrespective of the setting of the memory space enable